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| Keyword : FPGA
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Design Parameter Modeling for Design Space Exploration of Real-Time HDR Synthesis on FPGA
Masahiro NISHIMURA Taito MANABE Yuichiro SHIBATA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2026/03/01
Vol. E109-A
No. 3 ;
pp. 571-580
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
FPGA, HDR synthesis, design space exploration, | | | Summary | Full Text:PDF | |
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FPGA-Accelerated VXLAN Chaining for Partially Reconfigurable VNFs in Heterogeneous Data Centers
Yiwei CHANG Zhichuan GUO | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 2025/10/01
Vol. E108-B
No. 10 ;
pp. 1179-1189
Type of Manuscript:
PAPER
Category: Network
Keyword:
FPGA, VXLAN, VNF, OVS, heterogeneous data centers, | | | Summary | Full Text:PDF | |
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Performance and Power-Efficiency Improvements on Graph Embedding Using Sequential Training Algorithm and FPGA
Kazuki SUNAGA Keisuke SUGIURA Hiroki MATSUTANI | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2025/10/01
Vol. E108-D
No. 10 ;
pp. 1159-1169
Type of Manuscript:
PAPER
Category: Computer System
Keyword:
graph embedding, FPGA, OS-ELM, IoT, | | | Summary | Full Text:PDF | |
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An Embedded Intelligent System for Real-Time Image Classification with a Neuro-Inspired Color Constancy Algorithm
Akito MORITA Hirotsugu OKUNO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2025/06/01
Vol. E108-C
No. 6 ;
pp. 316-323
Type of Manuscript:
Special Section PAPER (Special Section on Low-Power and High-Speed Chips and Systems)
Category:
Keyword:
neuro-inspired, retinex, CNN, image recognition, FPGA, | | | Summary | Full Text:PDF | |
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An FPGA-Based YOLOv6 Accelerator for High-Throughput and Energy-Efficient Object Detection
Xingan SHA Masao YANAGISAWA Youhua SHI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2025/03/01
Vol. E108-A
No. 3 ;
pp. 473-481
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
object detection, CNN, YOLOv6, FPGA, accelerator, | | | Summary | Full Text:PDF | |
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Pipelined ADPCM Compression for HDR Synthesis on an FPGA
Masahiro NISHIMURA Taito MANABE Yuichiro SHIBATA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2024/03/01
Vol. E107-A
No. 3 ;
pp. 531-539
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design Technology and CAD
Keyword:
FPGA, HDR synthesis, image compression, | | | Summary | Full Text:PDF | |
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Real-Time Image-Based Vibration Extraction with Memory-Efficient Optical Flow and Block-Based Adaptive Filter
Taito MANABE Yuichiro SHIBATA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2023/03/01
Vol. E106-A
No. 3 ;
pp. 504-513
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
optical flow, feature matching, BMFLC, FPGA, real-time, | | | Summary | Full Text:PDF | |
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FPGA Implementation of a Stream-Based Real-Time Hardware Line Segment Detector
Taito MANABE Taichi KATAYAMA Yuichiro SHIBATA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2022/03/01
Vol. E105-A
No. 3 ;
pp. 468-477
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
line detection, stream processing, FPGA, real-time, | | | Summary | Full Text:PDF | |
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Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs
Akira JINGUJI Shimpei SATO Hiroki NAKAHARA | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2021/12/01
Vol. E104-D
No. 12 ;
pp. 2040-2047
Type of Manuscript:
Special Section PAPER (Special Section on Parallel, Distributed, and Reconfigurable Computing, and Networking)
Category:
Keyword:
CNN, sparse CNN, embedded system, FPGA, | | | Summary | Full Text:PDF | |
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HBDCA: A Toolchain for High-Accuracy BRAM-Defined CNN Accelerator on FPGA with Flexible Structure
Zhengjie LI Jiabao GAO Jinmei LAI | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2021/10/01
Vol. E104-D
No. 10 ;
pp. 1724-1733
Type of Manuscript:
PAPER
Category: Biocybernetics, Neurocomputing
Keyword:
toolchain, TensorFlow Lite, UpdateMEM, CNN, FPGA, | | | Summary | Full Text:PDF | |
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An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm
Keisuke SUGIURA Hiroki MATSUTANI | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2021/06/01
Vol. E104-D
No. 6 ;
pp. 789-800
Type of Manuscript:
PAPER
Category: Computer System
Keyword:
SLAM, GMapping, SoC, FPGA, | | | Summary | Full Text:PDF | |
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High-Performance and Hardware-Efficient Odd-Even Based Merge Sorter
Elsayed A. ELSAYED Kenji KISE | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2020/12/01
Vol. E103-D
No. 12 ;
pp. 2504-2517
Type of Manuscript:
Special Section PAPER (Special Section on Parallel, Distributed, and Reconfigurable Computing, and Networking)
Category: Computer System
Keyword:
FPGA, sorting, hardware merge sorter, odd-even sort, merge network, | | | Summary | Full Text:PDF | |
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FPGA Implementation and Evaluation of a Real-Time Image-Based Vibration Detection System with Adaptive Filtering
Taito MANABE Kazuya UETSUHARA Akane TAHARA Yuichiro SHIBATA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2020/12/01
Vol. E103-A
No. 12 ;
pp. 1472-1480
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
optical flow, Lucas-Kanade, BMFLC, FPGA, real-time, | | | Summary | Full Text:PDF | |
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Implementation and Area Optimization of LUT6 Based Convolution Structure on FPGA
Huangtao WU Wenjin HUANG Rui CHEN Yihua HUANG | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2019/12/01
Vol. E102-A
No. 12 ;
pp. 1813-1815
Type of Manuscript:
Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
FPGA, convolution circuits, area efficiency, | | | Summary | Full Text:PDF | |
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FPGA Implementation of a Real-Time Super-Resolution System Using Flips and an RNS-Based CNN
Taito MANABE Yuichiro SHIBATA Kiyoshi OGURI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2018/12/01
Vol. E101-A
No. 12 ;
pp. 2280-2289
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
FPGA, super-resolution, real-time, CNN, RNS, | | | Summary | Full Text:PDF | |
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A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA
Tomoya FUJII Shimpei SATO Hiroki NAKAHARA | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2018/02/01
Vol. E101-D
No. 2 ;
pp. 376-386
Type of Manuscript:
Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Emerging Applications
Keyword:
machine learning, deep learning, pruning, FPGA, | | | Summary | Full Text:PDF | |
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An Approach for Solving SAT/MaxSAT-Encoded Formal Verification Problems on FPGA
Kenji KANAZAWA Tsutomu MARUYAMA | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2017/08/01
Vol. E100-D
No. 8 ;
pp. 1807-1818
Type of Manuscript:
PAPER
Category: Computer System
Keyword:
FPGA, SAT, MaxSAT, WalkSAT, | | | Summary | Full Text:PDF | |
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Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA
Makoto SAEN Tadanobu TOBA Yusuke KANNO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2017/04/01
Vol. E100-C
No. 4 ;
pp. 382-390
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
FPGA, soft-error tolerance, memory controller, configuration RAM, | | | Summary | Full Text:PDF | |
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Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS Technology
Masakazu HIOKI Hanpei KOIKE | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D
No. 12 ;
pp. 3082-3089
Type of Manuscript:
PAPER
Category: Computer System
Keyword:
FPGA, programmable Vt, body biasing, static power, | | | Summary | Full Text:PDF | |
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The Reliability Analysis of the 1-out-of-2 System in Which Two Modules Do Mutual Cooperation in Recovery Mode
Aromhack SAYSANASONGKHAM Satoshi FUKUMOTO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/09/01
Vol. E99-A
No. 9 ;
pp. 1730-1734
Type of Manuscript:
LETTER
Category: Reliability, Maintainability and Safety Analysis
Keyword:
1-out-of-2 system, reliability analysis, Markov chain, unreliability, parallel redundant system, hardware restoration, data reconstruction, mutual cooperation, FPGA, reconfiguration, | | | Summary | Full Text:PDF | |
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Accelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique
Yusuke MATSUNAGA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A
No. 7 ;
pp. 1374-1380
Type of Manuscript:
Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category:
Keyword:
logic synthesis, technology mapping, FPGA, SAT, | | | Summary | Full Text:PDF | |
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Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration
Li-Chung HSU Masato MOTOMURA Yasuhiro TAKE Tadahiro KURODA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2015/04/01
Vol. E98-C
No. 4 ;
pp. 288-297
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
TCI, ThruChip, 3-D FPGA, TSV, FPGA, TPR, VPR, | | | Summary | Full Text:PDF | |
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A Digital TRNG Based on Cross Feedback Ring Oscillators
Lijuan LI Shuguo LI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/01/01
Vol. E97-A
No. 1 ;
pp. 284-291
Type of Manuscript:
Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Hardware Based Security
Keyword:
digital TRNG, FPGA, stateless, metastability, chaos, | | | Summary | Full Text:PDF | |
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Low Complexity Keypoint Extraction Based on SIFT Descriptor and Its Hardware Implementation for Full-HD 60 fps Video
Takahiro SUZUKI Takeshi IKENAGA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/06/01
Vol. E96-A
No. 6 ;
pp. 1376-1383
Type of Manuscript:
Special Section PAPER (Special Section on Circuit, System, and Computer Technologies)
Category:
Keyword:
keypoint extraction, SIFT, hardware implementation, FPGA, parallelizing, | | | Summary | Full Text:PDF | |
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Region Oriented Routing FPGA Architecture for Dynamic Power Gating
Ce LI Yiping DONG Takahiro WATANABE | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A
No. 12 ;
pp. 2199-2207
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword:
FPGA, low power, switch box, routing, | | | Summary | Full Text:PDF | |
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Asynchronous Circuit Design on Field Programmable Gate Array Devices
Jung-Lin YANG Shin-Nung LU Pei-Hsuan YU | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C
No. 4 ;
pp. 516-522
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
asynchronous, bundled-data, burst-mode, extended burst-mode, FPGA, generalized C-element, HDL, self-timed, | | | Summary | Full Text:PDF | |
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A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D
No. 2 ;
pp. 364-373
Type of Manuscript:
Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword:
regular expression, NFA, DFA, MNFAU, FPGA, | | | Summary | Full Text:PDF | |
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Hierarchical MFMO Circuit Modules for an Energy-Efficient SDR DBF
Jeich MAR Chi-Cheng KUO Shin-Ru WU You-Rong LIN | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D
No. 2 ;
pp. 413-425
Type of Manuscript:
Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Application
Keyword:
FPGA, MFMO, SDR, CR, ESPRIT, CORDIC, | | | Summary | Full Text:PDF | |
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FPGA Implementation of Metastability-Based True Random Number Generator
Hisashi HATA Shuichi ICHIKAWA | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D
No. 2 ;
pp. 426-436
Type of Manuscript:
Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Application
Keyword:
TRNG, synchronous digital circuit, FPGA, entropy, | | | Summary | Full Text:PDF | |
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Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher
Dai YAMAMOTO Kouichi ITOH Jun YAJIMA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A
No. 12 ;
pp. 2628-2638
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword:
block cipher, KASUMI, hardware, ASIC, FPGA, compact implementation, | | | Summary | Full Text:PDF | |
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Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture
Ce LI Yiping DONG Takahiro WATANABE | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A
No. 12 ;
pp. 2519-2527
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword:
FPGA, low power, power domain, power consumption, | | | Summary | Full Text:PDF | |
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High-Speed Passphrase Search System for PGP
Koichi SHIMIZU Daisuke SUZUKI Toyohiro TSURUMARU | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/01/01
Vol. E93-A
No. 1 ;
pp. 202-209
Type of Manuscript:
Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Application
Keyword:
passphrase, search, FPGA, PGP, security, | | | Summary | Full Text:PDF | |
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Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs
Taiga TAKATA Yusuke MATSUNAGA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A
No. 12 ;
pp. 3268-3275
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword:
FPGA, technology mapping, cut enumeration, | | | Summary | Full Text:PDF | |
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A Design of the Signal Processing Hardware Platform for Communication Systems
Byung Wook LEE Sung Ho CHO | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 2008/03/01
Vol. E91-B
No. 3 ;
pp. 939-942
Type of Manuscript:
LETTER
Category: Wireless Communication Technologies
Keyword:
OFDM, IEEE 802.16, FPGA, DSP, platform, | | | Summary | Full Text:PDF | |
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Basic Characteristics and Learning Potential of a Digital Spiking Neuron
Hiroyuki TORIKAI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/10/01
Vol. E90-A
No. 10 ;
pp. 2093-2100
Type of Manuscript:
Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: Neuron and Neural Networks
Keyword:
spiking neuron, digital dynamical system, learning, UWB, FPGA, | | | Summary | Full Text:PDF | |
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Implementation of Multi-Channel Modem for DSRC System on Signal Processing Platform for Software Defined Radio
Akihisa YOKOYAMA Hiroshi HARADA | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 2006/12/01
Vol. E89-B
No. 12 ;
pp. 3225-3232
Type of Manuscript:
Special Section PAPER (Special Section on Software Defined Radio Technology and Its Applications)
Category:
Keyword:
software defined radio, signal processing, FPGA, ITS, DSRC, | | | Summary | Full Text:PDF | |
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Fast FPGA-Emulation-Based Simulation Environment for Custom Processors
Yuichi NAKAMURA Kouhei HOSOKAWA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A
No. 12 ;
pp. 3464-3470
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation and Verification
Keyword:
custom processor, simulation, emulation, FPGA, | | | Summary | Full Text:PDF | |
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Frequency-Scaling Approach for Managing Power Consumption in NOCs
Chun-Lung HSU Wen-Tso WANG Ying-Fu HONG | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A
No. 12 ;
pp. 3580-3583
Type of Manuscript:
Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
frequency-scaling, low power, NOC, FPGA, | | | Summary | Full Text:PDF | |
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FPGA Design of Real-Time Watermarking Processor for 2DDWT-Based Video Compression
Young-Ho SEO Dong-Wook KIM | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/06/01
Vol. E87-A
No. 6 ;
pp. 1297-1304
Type of Manuscript:
Special Section PAPER (Special Section on Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003))
Category:
Keyword:
image watermarking, DWT, FPGA, hardware implementation, co-operation with compressor, | | | Summary | Full Text:PDF | |
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An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs
Yusuke MATSUNAGA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A
No. 12 ;
pp. 2715-2724
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword:
functional decomposition, BDDs, logic synthesis, FPGA, | | | Summary | Full Text:PDF | |
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Design of FIR Digital Filters with CSD Coefficients Having Power-of-Two DC Gain and Their FPGA Implementation for Minimum Critical Path
Mitsuru YAMADA Akinori NISHIHARA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/08/01
Vol. E84-A
No. 8 ;
pp. 1997-2003
Type of Manuscript:
PAPER
Category: Digital Signal Processing
Keyword:
FIR digital filters, CSD, optimization, integer programming, FPGA, | | | Summary | Full Text:PDF | |
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An Efficient Routing Algorithm for Symmetrical FPGAs Using Reliable Cost Metrics
Nak-Woong EUM Inhag PARK Chong-Min KYUNG | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/03/01
Vol. E84-A
No. 3 ;
pp. 829-838
Type of Manuscript:
PAPER
Category: VLSI Design Technology and CAD
Keyword:
FPGA, routing, routability, delay, | | | Summary | Full Text:PDF | |
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A Study on the Design of VME System Controller
Kang Hyeon RHEE | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A
No. 6 ;
pp. 1083-1090
Type of Manuscript:
Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category:
Keyword:
factory automaton, VME system controller, VHDL, FPGA, | | | Summary | Full Text:PDF | |
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Simplified Routing Procedure for a CAD-Verified FPGA
Takahiro MUROOKA Atsushi TAKAHARA Toshiaki MIYAZAKI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A
No. 11 ;
pp. 2440-2447
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
FPGA, CAD algorithms, routing, | | | Summary | Full Text:PDF | |
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Logic Synthesis for Cellular Architecture FPGAs Using EXOR Ternary Decision Diagrams
Gueesang LEE Sungju PARK | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A
No. 10 ;
pp. 1820-1825
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
logic synthesis, FPGA, Cellular architetcture, Maitra terms, ETDO, | | | Summary | Full Text:PDF | |
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Technology Mapping for FPGAs with Composite Logic Block Architectures
Hsien-Ho CHUANG C. Bernard SHUNG | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D
No. 10 ;
pp. 1396-1404
Type of Manuscript:
Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword:
technology mapping, FPGA, subject graph, pattern graph, | | | Summary | Full Text:PDF | |
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A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A
No. 3 ;
pp. 321-329
Type of Manuscript:
Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category:
Keyword:
FPGA, technology mapping, layout, path delay, performance optimization, | | | Summary | Full Text:PDF | |
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2 MIMO-OFDM System in 5.2-GHz Band