Hideyuki ITO


Dynamically Reconfigurable Logic LSI: PCA-2
Hideyuki ITO Ryusuke KONISHI Hiroshi NAKADA Hideyuki TSUBOI Yuichi OKUYAMA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/08/01
Vol. E87-D  No. 8  pp. 2011-2020
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Recornfigurable Systems
Keyword: 
dynamically reconfigurable hardwareautonomous reconfigurationasynchronous circuitparallel computing
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Dynamically Reconfigurable Logic LSI--PCA-1: The First Realization of the Plastic Cell Architecture
Hideyuki ITO Ryusuke KONISHI Hiroshi NAKADA Kiyoshi OGURI Minoru INAMORI Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/05/01
Vol. E86-D  No. 5  pp. 859-867
Type of Manuscript:  Special Section PAPER (Special Issue on Reconfigurable Computing)
Category: 
Keyword: 
reconfigurable computingautonomous reconfigurabilityasynchronous circuit design
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Programmable Dataflow Computing on PCA
Norbert IMLIG Tsunemichi SHIOZAWA Ryusuke KONISHI Kiyoshi OGURI Kouichi NAGAMI Hideyuki ITO Minoru INAMORI Hiroshi NAKADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2409-2416
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
programmable logic devicesdataflow computingparallel processingplastic cell architecture
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Plastic Cell Architecture: A Scalable Device Architecture for General-Purpose Reconfigurable Computing
Kouichi NAGAMI Kiyoshi OGURI Tsunemichi SHIOZAWA Hideyuki ITO Ryusuke KONISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9  pp. 1431-1437
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
reconfigurable computingFPGAsobject-orientedhardware description languagecellular automata
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Inverter Reduction Algorithm for Super Fine-Grain Parallel Processing
Hideyuki ITO Kouichi NAGAMI Tsunemichi SHIOZAWA Kiyoshi OGURI Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3  pp. 487-493
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
super fine-grain parallel processingFPGAhigh level synthesize PARTHENONinverter reductiondynamical system
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