Keyword : hardware acceleration


Hardware Accelerated Marking for Mark & Sweep Garbage Collection
Shinji KAWAMURA Tomoaki TSUMURA 
Publication:   
Publication Date: 2018/04/01
Vol. E101-D  No. 4 ; pp. 1107-1115
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
garbage collectionhardware accelerationmark & sweepenergy efficient implementation
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Enabling FPGA-as-a-Service in the Cloud with hCODE Platform
Qian ZHAO Motoki AMAGASAKI Masahiro IIDA Morihiro KUGA Toshinori SUEYOSHI 
Publication:   
Publication Date: 2018/02/01
Vol. E101-D  No. 2 ; pp. 335-343
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology and Platform
Keyword: 
FPGA-as-a-servicehardware accelerationopen-source hardware
 Summary | Full Text:PDF

FPGA Hardware Acceleration of a Phylogenetic Tree Reconstruction with Maximum Parsimony Algorithm
Henry BLOCK Tsutomu MARUYAMA 
Publication:   
Publication Date: 2017/02/01
Vol. E100-D  No. 2 ; pp. 256-264
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
FPGAhardware accelerationphylogenetic tree reconstructionmaximum parsimony
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Synthesis of Minimum-Cost Multilevel Logic Networks via Genetic Algorithm
Barry SHACKLEFORD Etsuko OKUSHI Mitsuhiro YASUDA Hisao KOIZUMI Katsuhiko SEO Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2528-2537
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
genetic algorithmlogic synthesishardware acceleration
 Summary | Full Text:PDF