Yuanwu LEI


Window Memory Layout Scheme for Alternate Row-Wise/Column-Wise Matrix Access
Lei GUO Yuhua TANG Yong DOU Yuanwu LEI Meng MA Jie ZHOU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/12/01
Vol. E96-D  No. 12  pp. 2765-2775
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
window memory layout scheme (WMLS)alternate row-wise/column-wise matrix accessSDRAMGPUFPGA
 Summary | Full Text:PDF

Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA
Rongchun LI Yong DOU Yuanwu LEI Shice NI Song GUO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2012/05/01
Vol. E95-B  No. 5  pp. 1602-1611
Type of Manuscript:  PAPER
Category: Fundamental Theories for Communications
Keyword: 
multi-standardradix-4Viterbi decoderFPGA
 Summary | Full Text:PDF

FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic
Yuanwu LEI Yong DOU Jie ZHOU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/11/01
Vol. E94-D  No. 11  pp. 2173-2183
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
variable-precision floating-point (VP) arithmeticVery Long Instruction Word (VLIW)elementary functionNewton's methodpolynomial approximationFPGA
 Summary | Full Text:PDF