Masayuki SATO


FLEXII: A Flexible Insertion Policy for Dynamic Cache Resizing Mechanisms
Masayuki SATO Ryusuke EGAWA Hiroyuki TAKIZAWA Hiroaki KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7  pp. 550-558
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
insertion policydynamic cache resizingenergy consumption
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MVP-Cache: A Multi-Banked Cache Memory for Energy-Efficient Vector Processing of Multimedia Applications
Ye GAO Masayuki SATO Ryusuke EGAWA Hiroyuki TAKIZAWA Hiroaki KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/11/01
Vol. E97-D  No. 11  pp. 2835-2843
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
vector architecturemultimedia applicationmulti-banked cache memory
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A Capacity-Aware Thread Scheduling Method Combined with Cache Partitioning to Reduce Inter-Thread Cache Conflicts
Masayuki SATO Ryusuke EGAWA Hiroyuki TAKIZAWA Hiroaki KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9  pp. 2047-2054
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
chip multiprocessorsshared cachesinter-thread cache conflictsthread schedulingcache partitioning
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A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks
Masatoshi NAKAMURA Masato INAGI Kazuya TANIGAWA Tetsuo HIRONAKA Masayuki SATO Takashi ISHIGURO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2  pp. 324-334
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
reconfigurable devicephysical designplacementroutingMPLDFPGAEDA
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Stuck-Open Fault Detectabilities of Various TPG Circuits for Use in Two-Pattern Testing
Kiyoshi FURUYA Susumu YAMAZAKI Masayuki SATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7  pp. 889-894
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
built-in self-test (BIST)two-pattern testfault coveragetransition coverage
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