FPGA-Based Hash Circuit Synthesis with Evolutionary Algorithms

Ernesto DAMIANI  Valentino LIBERALI  Andrea G. B. TETTAMANZI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E82-A   No.9   pp.1888-1896
Publication Date: 1999/09/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and Its Applications)
evolvable hardware,  evolutionary algorithms,  nonlinear circuit synthesis,  FPGA,  

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An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16-bit address space into an 8-bit one. The target technology is FPGA, where the search space of the algorithm is made of the combinational functions computed by cells and of the interconnections among cells. The evolutionary technique has been applied to five different interconnection topologies, specified by neighbourhood graphs. This circuit is readily applicable to the design of set-associative cache memories. Possible use of the evolutionary approach presented in the paper for on-line tuning of the function during cache operation is also discussed.