Tomonori IZUMI


Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device
Kentaro NAKAHARA Shin'ichi KOUYAMA Tomonori IZUMI Hiroyuki OCHI Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3612-3621
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
fault tolerancedependableFPGAreconfigurable devicesoft error
 Summary | Full Text:PDF

A Simulation Platform for Designing Cell-Array-Based Self-Reconfigurable Architecture
Shin'ichi KOUYAMA Tomonori IZUMI Hiroyuki OCHI Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A  No. 4  pp. 784-791
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
self-reconfigurationevaluation of architecturemodel of architecturesimulation
 Summary | Full Text:PDF

Fault Tolerant Dynamic Reconfigurable Device Based on EDAC with Rollback
Kentaro NAKAHARA Shin'ichi KOUYAMA Tomonori IZUMI Hiroyuki OCHI Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3652-3658
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
fault tolerancedependabledynamic reconfigurable
 Summary | Full Text:PDF

Design of Realtime 3-D Sound Processing System
Kosuke TSUJINO Kazuhiko FURUYA Wataru KOBAYASHI Tomonori IZUMI Takao ONOYE Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/05/01
Vol. E88-D  No. 5  pp. 954-962
Type of Manuscript:  Special Section PAPER (Special Section on Cyberworlds)
Category: 
Keyword: 
3-D soundvirtual realitysystem implementation
 Summary | Full Text:PDF

An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD
Tomonori IZUMI Shin'ichi KOUYAMA Hiroyuki OCHI Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4  pp. 907-914
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
reconfigurable systemdesign technologylogic synthesisvariable orderinglook-up table
 Summary | Full Text:PDF

Design Tools and Trial Designs for PCA-Chip2
Takuya OKAMOTO Takafumi YUASA Tomonori IZUMI Takao ONOYE Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/05/01
Vol. E86-D  No. 5  pp. 868-871
Type of Manuscript:  Special Section LETTER (Special Issue on Reconfigurable Computing)
Category: 
Keyword: 
Plastic Cell Architecturereconfigurable logicdesign automationcomputer aided design
 Summary | Full Text:PDF

LUT-Array-Based PLD and Synthesis Approach Based on Sum of Generalized Complex Terms Expression
Hiroshi TSUTSUI Akihiko TOMITA Shigenori SUGIMOTO Kazuhisa SAKAI Tomonori IZUMI Takao ONOYE Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2681-2689
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: FPGA Systhesis
Keyword: 
reconfigurable logicprogrammable logicsystem architecture and designlogic synthesissum of products
 Summary | Full Text:PDF

Array-Based Mapping Algorithm of Logic Functions into Plastic Cell Architecture
Tomonori IZUMI Ryuji KAN Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2538-2544
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
plastic cell architecturereconfigurable logictechnology mappinglayout
 Summary | Full Text:PDF

Air-Pressure Model and Fast Algorithms for Zero-Wasted-Area Layout of General Floorplan
Tomonori IZUMI Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/05/25
Vol. E81-A  No. 5  pp. 857-865
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
floorplanlayoutarea optimizationair-pressurezero-wasted-area
 Summary | Full Text:PDF

Computational Complexity Analysis of Set-Bin-Packing Problem
Tomonori IZUMI Toshihiko YOKOMARU Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/05/25
Vol. E81-A  No. 5  pp. 842-849
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
bin-packingcomplexitytechnology mappingFPGA
 Summary | Full Text:PDF