Kazushi KAWAMURA

Solving Constrained Slot Placement Problems Using an Ising Machine and Its Evaluations
Sho KANAMARU Kazushi KAWAMURA Shu TANAKA Yoshinori TOMITA Nozomu TOGAWA 
Publication:   
Publication Date: 2021/02/01
Vol. E104-D  No. 2  pp. 226-236
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
Ising machine, Ising model, slot-placement problem, quadratic assignment problem, quadratic unconstrained binary optimization, 
 Summary | Full Text:PDF
Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations
Koki ITO Kazushi KAWAMURA Yutaka TAMIYA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   
Publication Date: 2017/04/01
Vol. E100-A  No. 4  pp. 1015-1028
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
field-data extractor, multiplexer network, partitioning, rotator, 
 Summary | Full Text:PDF
Bi-Partitioning Based Multiplexer Network for Field-Data Extractors
Koki ITO Kazushi KAWAMURA Yutaka TAMIYA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7  pp. 1410-1414
Type of Manuscript:  Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
multiplexer network, partitioning, field-data extractor, 
 Summary | Full Text:PDF
Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs
Koichi FUJIWARA Kazushi KAWAMURA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7  pp. 1294-1310
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
interconnection delay, clock skew, high-level synthesis (HLS), FPGA, floorplan, 
 Summary | Full Text:PDF
A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs
Koichi FUJIWARA Kazushi KAWAMURA Shin-ya ABE Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7  pp. 1392-1405
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
high-level synthesis (HLS), FPGA, floorplan, interconnection delay, MUX, 
 Summary | Full Text:PDF
A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation
Kazushi KAWAMURA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/01/01
Vol. E96-A  No. 1  pp. 312-321
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
high-level synthesis, RDR, thermal-aware, hot spots, interconnect delays, 
 Summary | Full Text:PDF