IEICE SEARCH SYSTEM

Kazushi KAWAMURA

Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations Koki ITO Kazushi KAWAMURA Yutaka TAMIYA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2017/04/01 Vol. E100-A No. 4 pp. 1015-1028 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: field-data extractor, multiplexer network, partitioning, rotator,
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Bi-Partitioning Based Multiplexer Network for Field-Data Extractors Koki ITO Kazushi KAWAMURA Yutaka TAMIYA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 pp. 1410-1414 Type of Manuscript: Special Section LETTER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: multiplexer network, partitioning, field-data extractor,
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Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs Koichi FUJIWARA Kazushi KAWAMURA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 pp. 1294-1310 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: interconnection delay, clock skew, high-level synthesis (HLS), FPGA, floorplan,
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A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs Koichi FUJIWARA Kazushi KAWAMURA Shin-ya ABE Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 pp. 1392-1405 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis (HLS), FPGA, floorplan, interconnection delay, MUX,
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A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation Kazushi KAWAMURA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/01/01 Vol. E96-A No. 1 pp. 312-321 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: high-level synthesis, RDR, thermal-aware, hot spots, interconnect delays,
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