Masayuki IKEBE

FPGA-Based Annealing Processor with Time-Division Multiplexing
Kasho YAMAMOTO Masayuki IKEBE Tetsuya ASAI Masato MOTOMURA Shinya TAKAMAEDA-YAMAZAKI 
Publication:   
Publication Date: 2019/12/01
Vol. E102-D  No. 12  pp. 2295-2305
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Computer System
Keyword: 
ising model, annealing processor, simulated annealing, 
 Summary | Full Text:PDF
Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks
Kota ANDO Kodai UEYOSHI Yuka OBA Kazutoshi HIROSE Ryota UEMATSU Takumi KUDO Masayuki IKEBE Tetsuya ASAI Shinya TAKAMAEDA-YAMAZAKI Masato MOTOMURA 
Publication:   
Publication Date: 2019/12/01
Vol. E102-D  No. 12  pp. 2341-2353
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Computer System
Keyword: 
neural network, dithering, error diffusion, FPGA, hardware-oriented neural network algorithm, 
 Summary | Full Text:PDF
Evaluation of Digitally Controlled PLL by Clock-Period Comparison
Yukinobu MAKIHARA Masayuki IKEBE Eiichi SANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/06/01
Vol. E90-C  No. 6  pp. 1307-1310
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
digitally controlled PLL, clock-period comparator, loop characteristic, loop filter, 
 Summary | Full Text:PDF
CMOS Image Sensor Using Negative-Feedback Resetting to Obtain Variably Smoothed Images
Masayuki IKEBE Keita SAITO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1662-1669
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
CMOS-image sensor, negative feedback reset, filtersize, 
 Summary | Full Text:PDF