Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration

Li-Chung HSU  Masato MOTOMURA  Yasuhiro TAKE  Tadahiro KURODA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E98-C   No.4   pp.288-297
Publication Date: 2015/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E98.C.288
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
TCI,  ThruChip,  3-D FPGA,  TSV,  FPGA,  TPR,  VPR,  

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Summary: 
This paper presents work on integrating wireless 3-D interconnection interface, namely ThruChip Interface (TCI), in three-dimensional field-programmable gate array (3-D FPGA) exploration tool (TPR). TCI is an emerging 3-D IC integration solution because of its advantages over cost, flexibility, reliability, comparable performance, and energy dissipation in comparison to through-silicon-via (TSV). Since the communication bandwidth of TCI is much higher than FPGA internal logic signals, in order to fully utilize its bandwidth, the time-division multiplexing (TDM) scheme is adopted. The experimental results show 25% on average and 58% at maximum path delay reduction over 2-D FPGA when five layers are used in TCI based 3-D FPGA architecture. Although the performance of TCI based 3-D FPGA architecture is 8% below that of TSV based 3-D FPGA on average, TCI based architecture can reduce active area consumed by vertical communication channels by 42% on average in comparison to TSV based architecture and hence leads to better delay and area product.