Yoji KAJITANI


A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os
Masato INAGI Yasuhiro TAKASHIMA Yuichi NAKAMURA Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/05/01
Vol. E90-A  No. 5  pp. 924-931
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
circuit partitioningtime-multiplexed I/OFPGApin constraint
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The Oct-Touched Tile: A New Architecture for Shape-Based Routing
Ning FU Shigetoshi NAKATAKE Yasuhiro TAKASHIMA Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/02/01
Vol. E89-A  No. 2  pp. 448-455
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
analog layoutshape-based routingrouting architecturetile
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A Device-Level Placement with Schema Based Clusters in Analog IC Layouts
Takashi NOJIMA Xiaoke ZHU Yasuhiro TAKASHIMA Shigetoshi NAKATAKE Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3301-3308
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Analog Layout
Keyword: 
device-level placementrectangle packingSequence-Pairdirectional convexcluster-constraint
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EQ-Sequences for Coding Floorplans
Hua-An ZHAO Chen LIU Yoji KAJITANI Keishi SAKANUSHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3233-3243
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Floorplan
Keyword: 
floorplanplacementVLSI CADQ-sequence
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Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints
Ning FU Shigetoshi NAKATAKE Yasuhiro TAKASHIMA Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3224-3232
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Floorplan
Keyword: 
abstract floorplanconsistent floorplanpillar
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An Incremental Wiring Algorithm for VLSI Layout Design
Yukiko KUBO Shigetoshi NAKATAKE Yoji KAJITANI Masahiro KAWAKITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/05/01
Vol. E86-A  No. 5  pp. 1203-1206
Type of Manuscript:  Special Section LETTER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
wirabilityincremental wiringchannel intersection graphwire decomposition
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Recognition of Floorplan by Parametric BSG for Reuse of Layout Design
Keishi SAKANUSHI Zhonglin WU Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/04/01
Vol. E85-A  No. 4  pp. 872-879
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
parametric BSGlayoutreusefloorplantechnology migration
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An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm
Kengo R. AZEGAMI Masato INAGI Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/03/01
Vol. E85-A  No. 3  pp. 655-663
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
circuit partitionhyper-graph partitionnetwork flowmin-cutintegrated circuit design
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An Efficient Algorithm to Extract an Optimal Sub-Circuit by the Minimum Cut
Kengo R. AZEGAMI Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/05/01
Vol. E84-A  No. 5  pp. 1301-1308
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
circuit partitionhyper-graph partitionnetwork flowmin-cutintegrated circuit design
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The 3D-Packing by Meta Data Structure and Packing Heuristics
Hiroyuki YAMAZAKI Keishi SAKANUSHI Shigetoshi NAKATAKE Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/04/25
Vol. E83-A  No. 4  pp. 639-645
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
3D-packingplacementsequence-pairsequence-triplesimulated annealing
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Schedule-Clock-Tree Routing for Semi-Synchronous Circuits
Kazunori INOUE Wataru TAKAHASHI Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2431-2439
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
clock-treeclock-schedulingsemi-synchronous circuitdeferred-merge embedding
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Assignment of Intervals to Parallel Tracks with Minimum Total Cross-Talk
Yasuhiro TAKASHIMA Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/09/25
Vol. E81-A  No. 9  pp. 1909-1915
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
minimum cross-talkassignmentintersecting interval sets
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Air-Pressure Model and Fast Algorithms for Zero-Wasted-Area Layout of General Floorplan
Tomonori IZUMI Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/05/25
Vol. E81-A  No. 5  pp. 857-865
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
floorplanlayoutarea optimizationair-pressurezero-wasted-area
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Routability of FPGAs with Extremal Switch-Block Structures
Yasuhiro TAKASHIMA Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/05/25
Vol. E81-A  No. 5  pp. 850-856
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
FPGAswitch-blockroutabilitydetailed-routing
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Computational Complexity Analysis of Set-Bin-Packing Problem
Tomonori IZUMI Toshihiko YOKOMARU Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/05/25
Vol. E81-A  No. 5  pp. 842-849
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
bin-packingcomplexitytechnology mappingFPGA
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Cost-Radius Balanced Spanning/Steiner Trees
Hideki MITSUBAYASHI Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/04/25
Vol. E80-A  No. 4  pp. 689-694
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
delayspanning treesteiner treeVLSI layout
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Minimal Forbidden Minors for the Family of Graphs with Proper-Path-Width at Most Two
Atsushi TAKAHASHI Shuichi UENO Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12  pp. 1828-1839
Type of Manuscript:  PAPER
Category: Graphs and Networks
Keyword: 
proper-path-widthpath-widthminor-closed familyminimal forbidden minorVLSI layout
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Universal Graphs for Graphs with Bounded Path-Width
Atsushi TAKAHASHI Shuichi UENO Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/04/25
Vol. E78-A  No. 4  pp. 458-462
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
universal graphpath-widthk-pathparallel computing
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On the Proper-Path-Decomposition of Trees
Atsushi TAKAHASHI Shuichi UENO Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/01/25
Vol. E78-A  No. 1  pp. 131-136
Type of Manuscript:  LETTER
Category: Graphs, Networks and Matroids
Keyword: 
proper-path-widthproper-path-decompositionpath-widthpath-decompositionpolynomial time algorithm
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A Note on Dual Trail Partition of a Plane Graph
Shuichi UENO Katsufumi TSUJI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1991/07/25
Vol. E74-A  No. 7  pp. 1915-1917
Type of Manuscript:  LETTER
Category: Graphs, Networks and Matroids
Keyword: 
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A Note on the Graph Augmentation Problem
Shuichi UENO Katsufumi TSUJI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1991/04/25
Vol. E74-A  No. 4  pp. 679-680
Type of Manuscript:  Special Section LETTER (Special Issue on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
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FOREWORD
Sadatoshi KUMAGAI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1989/12/25
Vol. E72-E  No. 12  pp. 1277-1278
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
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A Switch-Box Router BOX-PEELER" and Its Tractable Problems
Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1989/12/25
Vol. E72-E  No. 12  pp. 1367-1373
Type of Manuscript:  Special Section PAPER (Special Issue on the 2nd Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology
Keyword: 
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Metric in the Set of Labelled Graphs and Its Applications to Network Theory
Yoji KAJITANI Hidekazu SAKURAI Eiji OKAMOTO 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1976/02/25
Vol. E59-E  No. 2  pp. 7-12
Type of Manuscript:  PAPER
Category: Network Theory
Keyword: 
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