For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Logic Synthesis for Look-Up Table Based FPGAs Using Functional Decomposition and Boolean Resubstitution
Hiroshi SAWADA Takayuki SUYAMA Akira NAGOYA
IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/10/25
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Design
FPGA, look-up table (LUT), functional decomposition, Boolean resubstitution, support minimization,
Full Text: PDF>>
This paper presents a logic synthesis method for look-up table (LUT) based field programmable gate arrays (FPGAs). We determine functions to be mapped to LUTs by functional decomposition for each of single-output functions. To share LUTs among several functions, we use a new Boolean resubstitution technique. Resubstitution is used to determine whether an existing function is useful to realize another function; thus, we can share common functions among two or more functions. The Boolean resubstitution proposed in this paper is customized for an LUT network synthesis because it is based on support minimization for an incompletely specified function. Experimental results show that our synthesis method produces a small size circuit in a practical amount of time.