Design Methods of Radix Converters Using Arithmetic Decompositions

Yukihiro IGUCHI  Tsutomu SASAO  Munehiro MATSUURA  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E90-D   No.6   pp.905-914
Publication Date: 2007/06/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e90-d.6.905
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Computer Components
Keyword: 
radix converter,  LUT cascades,  FPGA,  functional decomposition,  

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Summary: 
In arithmetic circuits for digital signal processing, radixes other than two are often used to make circuits faster. In such cases, radix converters are necessary. However, in general, radix converters tend to be complex. This paper considers design methods for p-nary to binary converters. First, it considers Look-Up Table (LUT) cascade realizations. Then, it introduces a new design technique called arithmetic decomposition by using LUTs and adders. Finally, it compares the amount of hardware and performance of radix converters implemented by FPGAs. 12-digit ternary to binary converters on Cyclone II FPGAs designed by the proposed method are faster than ones by conventional methods.