Akira NAGOYA


Dynamically Reconfigurable Logic LSI: PCA-2
Hideyuki ITO Ryusuke KONISHI Hiroshi NAKADA Hideyuki TSUBOI Yuichi OKUYAMA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/08/01
Vol. E87-D  No. 8  pp. 2011-2020
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Recornfigurable Systems
Keyword: 
dynamically reconfigurable hardwareautonomous reconfigurationasynchronous circuitparallel computing
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Dynamically Reconfigurable Logic LSI--PCA-1: The First Realization of the Plastic Cell Architecture
Hideyuki ITO Ryusuke KONISHI Hiroshi NAKADA Kiyoshi OGURI Minoru INAMORI Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/05/01
Vol. E86-D  No. 5  pp. 859-867
Type of Manuscript:  Special Section PAPER (Special Issue on Reconfigurable Computing)
Category: 
Keyword: 
reconfigurable computingautonomous reconfigurabilityasynchronous circuit design
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A Method of Mapping Finite State Machine into PCA Plastic Parts
Minoru INAMORI Hiroshi NAKADA Ryusuke KONISHI Akira NAGOYA Kiyoshi OGURI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/04/01
Vol. E85-A  No. 4  pp. 804-810
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
asynchronous designfinite state machinemappingprogrammable device
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A General Framework to Use Various Decomposition Methods for LUT Network Synthesis
Shigeru YAMASHITA Hiroshi SAWADA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2915-2922
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
functional decompositionalgebraic decompositionfield programmable gate array (FPGA)look-up table (LUT)
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An Efficient Implementation Method of a Metric Computation Accelerator for Fractal Image Compression Using Reconfigurable Hardware
Hidehisa NAGANO Akihiro MATSUURA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/01/01
Vol. E84-A  No. 1  pp. 372-377
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
fractal image compressionmetric computationreconfigurable hardwarepipeline processing
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Efficient Kernel Generation Based on Implicit Cube Set Representations and Its Applications
Hiroshi SAWADA Shigeru YAMASHITA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2513-2519
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
multi-level logic synthesissum-of-products expressionimplicit cube set representationkernel
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Restructuring Logic Representations with Simple Disjunctive Decompositions
Hiroshi SAWADA Shigeru YAMASHITA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2538-2544
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
simple disjunctive decompositionsymmetric variables ordered binary decision diagrammulti-level logic circuit
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An Efficient Method for Finding an Optimal Bi-Decomposition
Shigeru YAMASHITA Hiroshi SAWADA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2529-2537
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
functional decompositionbi-decompositionANDXORlook-up table
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Bit and Word-Level Common Subexpression Elimination for the Synthesis of Linear Computations
Akihiro MATSUURA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/03/25
Vol. E81-A  No. 3  pp. 455-461
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 10th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
high-level synthesiscommon subexpression eliminationlinear transformsmatrix decomposition
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Logic Synthesis for Look-Up Table Based FPGAs Using Functional Decomposition and Boolean Resubstitution
Hiroshi SAWADA Takayuki SUYAMA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/10/25
Vol. E80-D  No. 10  pp. 1017-1023
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Design
Keyword: 
FPGAlook-up table (LUT)functional decompositionBoolean resubstitutionsupport minimization
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A Hierarchical Clustering Method for the Multiple Constant Multiplication Problem
Akihiro MATSUURA Mitsuteru YUKISHITA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1767-1773
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
constant multiplicationMCM problemhigh-level synthesiscommon subexpression
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High-Level Synthesis Design at NTT Systems Labs
Yukihiro NAKAMURA Kiyoshi OGURI Akira NAGOYA Mitsuteru YUKISHITA Ryo NOMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9  pp. 1047-1054
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High-Level Design
Keyword: 
computer-hardware and disign
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