Keyword : memory controller


Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA
Makoto SAEN Tadanobu TOBA Yusuke KANNO 
Publication:   
Publication Date: 2017/04/01
Vol. E100-C  No. 4 ; pp. 382-390
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
FPGAsoft-error tolerancememory controllerconfiguration RAM
 Summary | Full Text:PDF

Deterministic Packet Buffer System with Multi FIFO Queues for the Advanced QoS
Hisashi IWAMOTO Yuji YANO Yasuto KURODA Koji YAMAMOTO Shingo ATA Kazunari INOUE 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2013/07/01
Vol. E96-B  No. 7 ; pp. 1819-1825
Type of Manuscript:  PAPER
Category: Network System
Keyword: 
packet buffermulti FIFO queuesmemory controllerquality services
 Summary | Full Text:PDF

Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs
Kohei HOSOKAWA Katsunori TANAKA Yuichi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2810-2817
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
FPGA-based hardware emulatorsSDRAMmemory controllerclock generator
 Summary | Full Text:PDF