A Graph Rewriting Approach for Converting Asynchronous ROMs into Synchronous Ones

Md. Nazrul Islam MONDAL  Koji NAKANO  Yasuaki ITO  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E94-D   No.12   pp.2378-2388
Publication Date: 2011/12/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E94.D.2378
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: 
Keyword: 
FPGA,  block RAMs,  asynchronous read operations,  rewriting algorithm,  

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Summary: 
Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read Only Memories (ROMs). Circuit design that minimizes the number of clock cycles is easy if we use asynchronous read operations. However, most of FPGAs support synchronous read operations, but do not support asynchronous read operations. The main contribution of this paper is to provide one of the potent approaches to resolve this problem. We assume that a circuit using asynchronous ROMs designed by a non-expert or quickly designed by an expert is given. Our goal is to convert this circuit with asynchronous ROMs into an equivalent circuit with synchronous ones. The resulting circuit with synchronous ROMs can be embedded into FPGAs. We also discuss several techniques to decrease the latency and increase the clock frequency of the resulting circuits.