An Analysis of Time Domain Reed Solomon Decoder with FPGA Implementation

Kentaro KATO  Somsak CHOOMCHUAY  

IEICE TRANSACTIONS on Information and Systems   Vol.E100-D   No.12   pp.2953-2961
Publication Date: 2017/12/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2017EDP7039
Type of Manuscript: PAPER
Category: Computer System
FPGA,  reed solomon decoder,  error correcting code,  time domain,  

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This paper analyzes the time domain Reed Solomon Decoder with FPGA implementation. Data throughput and area is carefully evaluated compared with typical frequency domain Reed Solomon Decoder. In this analysis, three hardware architecture to enhance the data throughput, namely, the pipelined architecture, the parallel architecture, and the truncated arrays, is evaluated, too. The evaluation reveals that the number of the consumed resources of RS(255, 239) is about 20% smaller than those of the frequency domain decoder although data throughput is less than 10% of the frequency domain decoder. The number of the consumed resources of the pipelined architecture is 28% smaller than that of the parallel architecture when data throughput is same. It is because the pipeline architecture requires less extra logics than the parallel architecture. To get higher data throughput, the pipelined architecture is better than the parallel architecture from the viewpoint of consumed resources.