Thi Diem TRAN


SLIT: An Energy-Efficient Reconfigurable Hardware Architecture for Deep Convolutional Neural Networks
Thi Diem TRAN Yasuhiko NAKASHIMA 
Publication:   
Publication Date: 2021/07/01
Vol. E104-C  No. 7  pp. 319-329
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
primary visual corteximage classificationconvolutional neural networkhardware architectureFPGAfeature extraction
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