Naoaki SUGANUMA


Pattern Generation for Locating Logic Design Errors
Masahiro TOMITA Naoaki SUGANUMA Kotaro HIRANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/05/25
Vol. E77-A  No. 5  pp. 881-893
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
binary decision diagrampattern generationlogic diagnosisrectificationlogic verification
 Summary | Full Text:PDF

Reconfigurable Machine and its Application to Logic Simulation
Nasahiro TOMITA Naoaki SUGANUMA Kotaro HIRANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1705-1712
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
reconfigurable machinelogic simulationFPGAhardware accelerator
 Summary | Full Text:PDF

A Logic Diagnosis Technique for Multiple Output Circuit
Naoaki SUGANUMA Nobuto UEDA Masahiro TOMITA Kotaro HIRANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10  pp. 1263-1271
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic diagnosislogic error locationlogic verificationEXM-algorithm
 Summary | Full Text:PDF