Keyword : instruction set


A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core
Osamu NISHII Yoichi YUYAMA Masayuki ITO Yoshikazu KIYOSHIGE Yusuke NITTA Makoto ISHIKAWA Tetsuya YAMADA Junichi MIYAKOSHI Yasutaka WADA Keiji KIMURA Hironori KASAHARA Hideo MAEJIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4 ; pp. 663-669
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
heterogeneousinstruction setMMU
 Summary | Full Text:PDF

Diversification of Processors Based on Redundancy in Instruction Set
Shuichi ICHIKAWA Takashi SAWADA Hisashi HATA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/01/01
Vol. E91-A  No. 1 ; pp. 211-220
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Implementation
Keyword: 
FPGAembedded systemsinstruction setrandomizationsecure processor
 Summary | Full Text:PDF