Yukihiro IGUCHI


A Method to Find Linear Decompositions for Incompletely Specified Index Generation Functions Using Difference Matrix
Tsutomu SASAO Yuta URANO Yukihiro IGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2427-2433
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
minimal coverlinear transformationfunctional decompositionincompletely specified functionlogic minimization
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Design Methods of Radix Converters Using Arithmetic Decompositions
Yukihiro IGUCHI Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/06/01
Vol. E90-D  No. 6  pp. 905-914
Type of Manuscript:  PAPER
Category: Computer Components
Keyword: 
radix converterLUT cascadesFPGAfunctional decomposition
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A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGA
Hui QIN Tsutomu SASAO Yukihiro IGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/03/01
Vol. E89-D  No. 3  pp. 1139-1147
Type of Manuscript:  PAPER
Category: Computer Components
Keyword: 
AES encryptionpipelined partial rolling (PPR)FPGA
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A Realization of Multiple-Output Functions by a Look-Up Table Ring
Hui QIN Tsutomu SASAO Munehiro MATSUURA Shinobu NAGAYAMA Kazuyuki NAKAMURA Yukihiro IGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3141-3150
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
LUT cascadeLUT ringmultiple-output functionreconfigurable logicprogrammable logic device
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Area-Time Complexities of Multi-Valued Decision Diagrams
Shinobu NAGAYAMA Tsutomu SASAO Yukihiro IGUCHI Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/05/01
Vol. E87-A  No. 5  pp. 1020-1028
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
decision diagramsthe number of nodesarea-time complexityrandomly generated functionrepresentation of logic functions
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Fault Diagnosis for RAMs Using Walsh Spectrum
Atsumu ISENO Yukihiro IGUCHI Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3  pp. 592-600
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Memory Testing
Keyword: 
memory testdiagnosisBISTfail-bitmapWalsh spectrum
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Bi-Partition of Shared Binary Decision Diagrams
Munehiro MATSUURA Tsutomu SASAO Jon T. BUTLER Yukihiro IGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2693-2700
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
shared binary decision diagramSBDDbi-partitionmultiple-output functiondecomposition
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On Properties of Kleene TDDs
Yukihiro IGUCHI Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 716-723
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Logic Simulation and Logic Optimization
Keyword: 
binary decision diagramternary decision diagramlogic simulationternary logic
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