Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture

Cao LIANG  Xinming HUANG  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E93-C   No.3   pp.407-415
Publication Date: 2010/03/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.407
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
coarse-grained reconfigurable architecture,  parallel FFT,  energy efficiency,  ASIC,  FPGA,  DSP,  

Full Text: PDF>>
Buy this Article




Summary: 
Fast Fourier Transform (FFT) is an important algorithm in many digital signal processing applications, and it often requires parallel implementation for high throughput. In this paper, we first present the SmartCell coarse-grained reconfigurable architecture targeted for stream processing. A SmartCell prototype integrates 64 processing elements, configurable interconnections, and dedicated instruction and data memories into a single chip, which is able to provide high performance parallel processing while maintaining post-fabrication flexibility. Subsequently, we present a parallel FFT architecture targeted for multi-core platforms computing systems. This algorithm provides an optimized data flow pattern that reduces both communication and configuration overheads. The proposed parallel FFT algorithm is then mapped onto the SmartCell prototype device. Results show that the parallel FFT implementation on SmartCell is about 14.9 and 2.7 times faster than network-on-chip (NoC) and MorphoSys implementations, respectively. SmartCell also achieves the energy efficiency gains of 2.1 and 28.9 when compared with FPGA and DSP implementations.