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Logic Synthesis for Cellular Architecture FPGAs Using EXOR Ternary Decision Diagrams
Gueesang LEE Sungju PARK
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
logic synthesis, FPGA, Cellular architetcture, Maitra terms, ETDO,
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In this paper, an efficient approach to the synthesis of CA (Cellular Architecture) -type FPGAs is presented. To exploit the array structure of cells in CA-type FPGAs, logic expressions called Maitra terms which can be mapped directly to the cell arrays are generated by using ETDDs (EXOR Ternary Decision Diagrams). Since a traversal of the ETDD is sufficient to generate a Maitra term which takes O (n) steps where n is the number of nodes in the ETDD, Maitra terms are generated very efficiently. The experiments show that the proposed method generates better results than existing methods.