Keyword : logic simulation


Representations of Multiple-Output Functions Using Binary Decision Diagrams for Characteristic Functions
Hafiz Md. HASAN BABU Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2398-2406
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
binary decision diagram (BDD)characteristic function (CF)multiple-output functionvariable orderinglogic simulationadderbit-counting functionmultiplier
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A Technique for Modelling Dynamic Reconfiguration with Improved Simulation Accuracy
Milan VASILKO David CABANIS 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2465-2474
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic simulationDynamically Reconfigurable Logicrun-time reconfigurationVHDLFPGAs
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Shared Multi-Terminal Binary Decision Diagrams for Multiple-Output Functions
Hafiz Md. HASAN BABU Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2545-2553
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
binary decision diagram (BDD)multiple-output functions clique coverTDM realizationlogic simulation
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On Properties of Kleene TDDs
Yukihiro IGUCHI Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 716-723
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Logic Simulation and Logic Optimization
Keyword: 
binary decision diagramternary decision diagramlogic simulationternary logic
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Guided-Probe Diagnosis of LSIs Containing Macrocells
Norio KUJI Tadao TAKEDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 731-737
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Beam Testing/Diagnosis
Keyword: 
electron beam testerguided-probe diagnosismacrocellmemory macrologic simulationlogic modelCAD navigation
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A CAD-Based Approach to Fault Diagnosis of CMOS LSI with Single Fault Using Abnormal Iddq
Masaru SANADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1945-1954
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
CMOSLSIIddqsingle faulty modefault diagnosislogic simulation
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Cone/Block Methods for Logic Simulation Time Reduction in E-Beam Guided-Probe Diagnosis
Norio KUJI Kazuhiro SHIRAKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/04/25
Vol. E77-C  No. 4 ; pp. 560-566
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Failure Analysis)
Category: 
Keyword: 
logic simulationcone/block methodsguide-probe diagnosiselectron beam testing
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Reconfigurable Machine and its Application to Logic Simulation
Nasahiro TOMITA Naoaki SUGANUMA Kotaro HIRANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10 ; pp. 1705-1712
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
reconfigurable machinelogic simulationFPGAhardware accelerator
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Research Topics and Results on Simulation for VLSI
Isao SHIRAKAWA Nagisa ISHIURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/07/25
Vol. E76-A  No. 7 ; pp. 1070-1076
Type of Manuscript:  Special Section PAPER (Special Section on Surveys of Researches in CAS Fields in the Last Two Decades, I)
Category: 
Keyword: 
VLSIcircuit simulationlogic simulation
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Timing Verification of Logic Circuits with Combined Delay Model
Shinji KIMURA Shigemi KASHIMA Hiromasa HANEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10 ; pp. 1230-1238
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
timing verificationcomputer aided designlogic simulation
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