A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications

Konstantinos SIOZIOS  George KOUTROUMPEZIS  Konstantinos TATAS  Nikolaos VASSILIADIS  Vasilios KALENTERIDIS  Haroula POURNARA  Ilias PAPPAS  Dimitrios SOUDRIS  Antonios THANAILAKIS  Spiridon NIKOLAIDIS  Stilianos SISKOS  

IEICE TRANSACTIONS on Information and Systems   Vol.E88-D   No.7   pp.1369-1380
Publication Date: 2005/07/01
Online ISSN: 
DOI: 10.1093/ietisy/e88-d.7.1369
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Programmable Logic, VLSI, CAD and Layout
FPGA,  circuit design,  CAD tools,  RTL design,  configuration bitstream,  

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A complete system for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform is introduced. The novel power-efficient FPGA architecture was designed and simulated in STM 0.18 µm CMOS technology. The detailed design and circuit characteristics of the Configurable Logic Block, the interconnection network, the switch box and the connection box were determined and evaluated in terms of energy, delay and area. A number of circuit-level low-power techniques were employed because power consumption was the primary concern. Additionally, a complete tool framework for the implementation of digital logic circuits in FPGA platforms is introduced. Having as input VHDL description of an application, the framework derives the reconfiguration bitstream of FPGA. The framework consists of: i) non-modified academic tools, ii) modified academic tools and iii) new tools. Furthermore, the framework can support a variety of FPGA architectures. Qualitative and quantitative comparisons with existing academic and commercial architectures and tools are provided, yielding promising results.