Chong-Min KYUNG


Power Minimization for Dual- and Triple-Supply Digital Circuits via Integer Linear Programming
Ki-Yong AHN Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/09/01
Vol. E92-A  No. 9  pp. 2318-2325
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
system on chiplow power designpartitioninginteger linear programming
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An Automatic Interface Insertion Scheme for In-System Verification of Algorithm Models in C
Chang-Jae PARK Ando KI In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2645-2654
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High Level Synthesis
Keyword: 
automatic interface insertionin-system verificationsource-to-source translation
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Issues on the Interface Synthesis between Intellectual Properties Operating at Different Clock Frequencies
Bong-Il PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/08/01
Vol. E85-A  No. 8  pp. 1937-1945
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
interface synthesisprotocol conversionintellectual property
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An Efficient Routing Algorithm for Symmetrical FPGAs Using Reliable Cost Metrics
Nak-Woong EUM Inhag PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/03/01
Vol. E84-A  No. 3  pp. 829-838
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
FPGAroutingroutabilitydelay
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Synthesis of Application-Specific Coprocessor for Core-Based ASIC Design
Dae-Hyun LEE In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/02/01
Vol. E84-A  No. 2  pp. 604-613
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
core-based designhardware/software codesigncoprocessor
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CLASSIC: An O(n2)-Heuristic Algorithm for Microcode Bit Optimization Based on Incompleteness Relations
Young-doo CHOI In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/05/25
Vol. E83-A  No. 5  pp. 901-908
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
control memoryheuristic algorithminstruction memorymicroprogrammingminimization
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A New Single-Clock Flip-Flop for Half-Swing Clocking
Young-Su KWON In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2521-2526
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
low power circuitclocking powerhalf-swing clocking
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Improving Dictionary-Based Code Compression in VLIW Architectures
Sang-Joon NAM In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2318-2324
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
code compressionVLIW architecture
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Path-Classified Trace Cache for Improving Hit Ratio in Wide-Issue Processors
Jin-Hyuk YANG In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/10/25
Vol. E82-D  No. 10  pp. 1338-1343
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
superscalarinstruction fetchtrace cache
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A Hierarchical Circuit Clustering Algorithm with Stable Performance
Seung-June KYOUNG Kwang-Su SEONG In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/09/25
Vol. E82-A  No. 9  pp. 1987-1993
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
VLSICADpartitioningclustering
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Fast Precise Interrupt Handling without Associative Searching in Multiple Out-Of-Order Issue Processors
Sang-Joon NAM In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/03/25
Vol. E82-D  No. 3  pp. 645-653
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
computer architectureprecise interruptmultiple out-of-order issue processors
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SAPICE: A Design Tool of CMOS Operational Amplifiers
Sang-Dae YU Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/09/25
Vol. E80-A  No. 9  pp. 1667-1675
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
operational amplifier designsimulated annealingcircuit optimization.
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SEWD: A Cache Architecture to Speed up the Misaligned Instruction Prefetch
Joon-Seo YIM In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/07/25
Vol. E80-D  No. 7  pp. 742-745
Type of Manuscript:  LETTER
Category: Computer Hardware and Design
Keyword: 
cachemicroprocessorpipeline
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Spread Omega Network for High Speed Packet Switching
H. C. LEE Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1997/01/25
Vol. E80-B  No. 1  pp. 192-195
Type of Manuscript:  LETTER
Category: Switching and Communication Processing
Keyword: 
telecommunicationswitchingnetworksspreadomega
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A Clustering Based Linear Ordering Algorithm for Netlist Partitioning
Kwang-Su SEONG Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A  No. 12  pp. 2185-2191
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
netlist partitioningspectral methodlinear ordering
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A Supplementary Scheme for Reducing Cache Access Time
Jong-Hong BAE Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/04/25
Vol. E79-D  No. 4  pp. 385-387
Type of Manuscript:  LETTER
Category: Computer Hardware and Design
Keyword: 
computer architecturecachepenalty cyclespipeline
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Fast Image Generation Method for Animation
Jin-Han KIM Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/06/25
Vol. E75-A  No. 6  pp. 691-700
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1991 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC '91))
Category: Combinational/Numerical/Graphic Algorithms
Keyword: 
computer graphicsimage classificationimage interpolation
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Hardware Accelerator for Outline Font Generation
Gyu-Cheol HWANG In-Cheol PARK Yun-Tae LEE Tae-Hyung LEE Jong-Hong BAE Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1991/10/25
Vol. E74-A  No. 10  pp. 3078-3082
Type of Manuscript:  Special Section PAPER (Special Issue on JTC-CSCC '90)
Category: VLSI Design Technology
Keyword: 
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