Keyword : SAT


A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT
Masayoshi YOSHIMURA Yoshiyasu TAKAHASHI Hiroshi YAMAZAKI Toshinori HOSOKAWA 
Publication:   
Publication Date: 2017/12/01
Vol. E100-A  No. 12 ; pp. 2824-2833
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
transition faultscorrelationcapture power reductionX-fillingSAT
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An Approach for Solving SAT/MaxSAT-Encoded Formal Verification Problems on FPGA
Kenji KANAZAWA Tsutomu MARUYAMA 
Publication:   
Publication Date: 2017/08/01
Vol. E100-D  No. 8 ; pp. 1807-1818
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
FPGASATMaxSATWalkSAT
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A Test Pattern Compaction Method Using SAT-Based Fault Grouping
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12 ; pp. 2302-2309
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
ATPGSATtest pattern
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Accelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7 ; pp. 1374-1380
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
logic synthesistechnology mappingFPGASAT
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Using Satisfiability Solving for Pairwise Testing in the Presence of Constraints
Toru NANBA Tatsuhiro TSUCHIYA Tohru KIKUNO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/09/01
Vol. E95-A  No. 9 ; pp. 1501-1505
Type of Manuscript:  Special Section LETTER (Special Section on Software Reliability Engineering)
Category: 
Keyword: 
SATsoftware testingpairwise testingtest set generationconstraints
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Solving SAT and Hamiltonian Cycle Problem Using Asynchronous P Systems
Hirofumi TAGAWA Akihiro FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/03/01
Vol. E95-D  No. 3 ; pp. 746-754
Type of Manuscript:  Special Section PAPER (Special Section on Foundations of Computer Science – Mathematical Foundations and Applications of Computer Science and Algorithms –)
Category: 
Keyword: 
membrane computingasynchronous parallelismSATHamiltonian cycle problem
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Accelerating Boolean Matching Using Bloom Filter
Chun ZHANG Yu HU Lingli WANG Lei HE Jiarong TONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/10/01
Vol. E93-A  No. 10 ; pp. 1775-1781
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
FPGABoolean matchingBloom filterSATre-synthesis
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Constrained Stimulus Generation with Self-Adjusting Using Tabu Search with Memory
Yanni ZHAO Jinian BIAN Shujun DENG Zhiqiu KONG Kang ZHAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3086-3093
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verfication
Keyword: 
constrained random simulationstimulus generationSATpiecewise-uniformtabu search with memory
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Detecting a Singleton Attractor in a Boolean Network Utilizing SAT Algorithms
Takeyuki TAMURA Tatsuya AKUTSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/02/01
Vol. E92-A  No. 2 ; pp. 493-501
Type of Manuscript:  PAPER
Category: Algorithms and Data Structures
Keyword: 
Boolean networksingleton attractorfixed pointSATNP-hard
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High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability
Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3293-3300
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
high speedcell layout synthesisBoolean SatisfiabilitySATCMOS logic cellminimum width
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Feature Interaction Detection by Bounded Model Checking
Tomoyuki YOKOGAWA Tatsuhiro TSUCHIYA Masahide NAKAMURA Tohru KIKUNO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12 ; pp. 2579-2587
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Dependable Communication
Keyword: 
bounded model checkingSATfeature interaction
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Solving SAT Efficiently with Promises
Kazuo IWAMA Akihiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/02/01
Vol. E86-D  No. 2 ; pp. 213-218
Type of Manuscript:  Special Section PAPER (Special Issue on Selected Papers from LA Symposium)
Category: Turing Machine, Recursive Functions
Keyword: 
SATCNF formulapromisesolution-densityinclusion-exclusion
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NP-Completeness of Reallocation Problems with Restricted Block Volume
Hiroyoshi MIWA Hiro ITO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/04/25
Vol. E83-A  No. 4 ; pp. 590-597
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
reallocationcomputational complexityNP-completeSATsteiner tree problem
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