For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
FPGA Design of User Monitoring System for Display Power Control
Tomoaki ANDO Vasily G. MOSHNYAGA Koji HASHIMOTO
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
seven-segment rectangular template, between the eyes region, eye-detection, user monitoring, FPGA, display, power management,
Full Text: PDF>>
This paper introduces new FPGA design of user-monitoring system for power management of PC display. From the camera readings the system detects whether the user looks at the screen or not and produces signals to control the display backlight. The system provides over 88% eye detection accuracy at 8f/s image processing rate. We describe new eye-tracking algorithm and hardware and present the results of its experimental evaluation in prototype display power management system.