Luca FANUCCI


A Configurable Hardware Word Re-Ordering Block for Multi-Lane Communication Protocols: Design and Use Case
Pietro NANNIPIERI Gianmarco DINELLI Luca FANUCCI 
Publication:   
Publication Date: 2019/05/01
Vol. E102-A  No. 5  pp. 747-749
Type of Manuscript:  LETTER
Category: Communication Theory and Signals
Keyword: 
VLSImulti-lanehigh-speedword re-orderingSpaceFibre
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VHDL Design of a SpaceFibre Routing Switch
Alessandro LEONI Pietro NANNIPIERI Luca FANUCCI 
Publication:   
Publication Date: 2019/05/01
Vol. E102-A  No. 5  pp. 729-731
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
SpaceFibreSpaceWireRoutingSwitchsatellite networksFPGA
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A Novel Parallel 8B/10B Encoder: Architecture and Comparison with Classical Solution
Pietro NANNIPIERI Daniele DAVALLE Luca FANUCCI 
Publication:   
Publication Date: 2018/07/01
Vol. E101-A  No. 7  pp. 1120-1122
Type of Manuscript:  LETTER
Category: Digital Signal Processing
Keyword: 
VLSI8b10bparallelencoding
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Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters
Sergio SAPONARA Pierluigi NUZZO Claudio NANI Geert VAN DER PLAS Luca FANUCCI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/06/01
Vol. E92-C  No. 6  pp. 843-851
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
A/D converterstime interleavinganalog CMOS circuitssystem level designSARlow power design
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Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems
Nicola E. L'INSALATA Sergio SAPONARA Luca FANUCCI Pierangelo TERRENI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 487-496
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
FFTOFDM communication systemconfigurable macrocellIP reuse
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VLSI Design of a Fully-Parallel High-Throughput Decoder for Turbo Gallager Codes
Luca FANUCCI Pasquale CIAO Giulio COLAVOLPE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/07/01
Vol. E89-A  No. 7  pp. 1976-1986
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
low-density parity-check (LDPC) codesbelief propagationiterative decodingVLSI architecturesparallel decoder architectures
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High-Throughput Multi-Rate Decoding of Structured Low-Density Parity-Check Codes
Luca FANUCCI Massimo ROVINI Nicola E. L'INSALATA Francesco ROSSI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3539-3547
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
low-density parity-checkstructured codesmulti-rate decodershigh-throughput architecturevectorised architectureWLAN
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Self-Adaptive Algorithmic/Architectural Design for Real-Time, Low-Power Video Systems
Luca FANUCCI Sergio SAPONARA Massimiliano MELANI Pierangelo TERRENI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1538-1545
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Adaptive Signal Processing
Keyword: 
adaptive signal processinglow-powerVLSI architecturesimage processing and multimedia systemsH.264
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Power Optimization of an 8051-Compliant IP Microcontroller
Luca FANUCCI Sergio SAPONARA Alexander MORELLO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 597-600
Type of Manuscript:  Special Section LETTER (Special Section on Low-Power LSI and Low-Power IP)
Category: 
Keyword: 
low-powerVLSIintellectual property (IP) cells8051 microcontroller
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Coupling-Driven Data Bus Encoding for SoC Video Architectures
Luca FANUCCI Riccardo LOCATELLI Andrea MINGHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3083-3090
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
bus encodingdeep sub-micronlow powersystem-on-chipvideo codingvery large scale integration architectures
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Low Complexity Detection for UTRA-TDD Receivers
Luca FANUCCI Riccardo GRASSO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/03/01
Vol. E87-A  No. 3  pp. 666-673
Type of Manuscript:  Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing)
Category: Communication Theory and Systems
Keyword: 
UTRA-TDDTD-CDMAMMSEFFT
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RFI Cancellation in DMT VDSL: A Digital Frequency Domain Scheme
Riccardo LOCATELLI Silvia BRINI Luca FANUCCI Christophe Del TOSO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/08/01
Vol. E86-A  No. 8  pp. 1993-2000
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
very high speed digital subscriber linediscrete multitoneradio frequency interference cancellationnarrowband interferer
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Multi-Code Multi-Carrier CDMA Modulation with Adaptive Bit-Loading for VDSL Modems
Massimo ROVINI Giovanni VANINI Luca FANUCCI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/08/01
Vol. E86-A  No. 8  pp. 1985-1992
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
very-high speed digital subscriber linemulti-code multi-carrier code division multiple accessbit loadingchannel throughput
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Data Driven Power Saving for DCT/IDCT VLSI Macrocell
Luca FANUCCI Sergio SAPONARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/07/01
Vol. E85-A  No. 7  pp. 1760-1765
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
very large scale integration architectureslow power designdesign reuseclock gatingvideo coding
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A Low-Complexity and High-Resolution Algorithm for the Magnitude Approximation of Complex Numbers
Luca FANUCCI Massimo ROVINI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/07/01
Vol. E85-A  No. 7  pp. 1766-1769
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
complex numbermagnitude approximationpower estimationhardware implementationVLSI
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