Keyword : HDL


Asynchronous Circuit Design on Field Programmable Gate Array Devices
Jung-Lin YANG Shin-Nung LU Pei-Hsuan YU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 516-522
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
asynchronousbundled-databurst-modeextended burst-modeFPGAgeneralized C-elementHDLself-timed
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HDLs Modeling Technique for Burst-Mode and Extended Burst-Mode Asynchronous Circuits
Jung-Lin YANG Jau-Cheng WEI Shin-Nung LU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12 ; pp. 2590-2599
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
asynchronousburst-modeextended burst-modeHDLhandshake packageVHDLVerilogself-timed
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Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique
Nobuhiro DOI Takashi HORIYAMA Masaki NAKANISHI Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3427-3434
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
HDLhigh-level synthesisbit-length optimizationnon-linear programming
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Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis
Nobuhiro DOI Takashi HORIYAMA Masaki NAKANISHI Shinji KIMURA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3184-3191
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic and High Level Synthesis
Keyword: 
HDLhigh-level synthesisparallelizing compilerbit length
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New Trend and Future Issues of Hardware Description Language and High-Level Synthesis
Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A  No. 3 ; pp. 307-313
Type of Manuscript:  INVITED PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
HDLhigh-level synthesisVHDLverilog HDLUDL/IPARTHENONSFL
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