Keyword : Networks-on-Chip

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip
Yuan HE Masaaki KONDO Takashi NAKADA Hiroshi SASAKI Shinobu MIWA Hiroshi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12 ; pp. 2881-2890
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
Networks-on-Chip, performance, energy efficiency, optimization, selection, 
 Summary | Full Text:PDF
A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs
Daihan WANG Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/12/01
Vol. E90-D  No. 12 ; pp. 1914-1922
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Reconfigurable System and Applications
Keyword: 
Networks-on-Chip, FPGA, router, port combination, 
 Summary | Full Text:PDF