Keyword : body biasing


A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation
Koki IGAWA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   
Publication Date: 2017/07/01
Vol. E100-A  No. 7 ; pp. 1439-1451
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
high-level synthesisdelay variationbody biasinginterconnection delayfloorplan
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Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS Technology
Masakazu HIOKI Hanpei KOIKE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12 ; pp. 3082-3089
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
FPGAprogrammable Vtbody biasingstatic power
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A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning
Shuta KIMURA Masanori HASHIMOTO Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2292-2300
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
post-silicon tuningbody bias clusteringprocess variationbody biasingstatistical static timing analysis
 Summary | Full Text:PDF