Yoshiya KOMATSU


Architecture of an Asynchronous FPGA for Handshake-Component-Based Design
Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8  pp. 1632-1644
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
FPGAreconfigurable LSIself-timed circuitasynchronous circuit
 Summary | Full Text:PDF

Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture
Shota ISHIHARA Ryoto TSUCHIYA Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/10/01
Vol. E94-C  No. 10  pp. 1669-1679
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
mixed synchronous/asynchronous designreconfigurable VLSIfour-phase dual-rail encodingself-timed architectureGALS (Globally Asynchronous Locally Synchronous)
 Summary | Full Text:PDF

An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture
Shota ISHIHARA Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/08/01
Vol. E93-C  No. 8  pp. 1338-1348
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
reconfigurable VLSIfield-programmable VLSILEDR (Level-Encoded Dual-Rail) encoding4-phase dual-rail encodingself-timed architecture
 Summary | Full Text:PDF