Keyword : physical design


A Novel High-Performance Heuristic Algorithm with Application to Physical Design Optimization
Yiqiang SHENG Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12 ; pp. 2418-2426
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
NP-hard problemoptimizationconflicting objectivesphysical designplacement
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Trojan Vulnerability Map: An Efficient Metric for Modeling and Improving the Security Level of Hardware
Mahmoud BAKHSHIZADEH Ali JAHANIAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/11/01
Vol. E97-A  No. 11 ; pp. 2218-2226
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
hardware securityhardware trojanphysical design
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A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks
Masatoshi NAKAMURA Masato INAGI Kazuya TANIGAWA Tetsuo HIRONAKA Masayuki SATO Takashi ISHIGURO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2 ; pp. 324-334
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
reconfigurable devicephysical designplacementroutingMPLDFPGAEDA
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Accurate Systematic Hot-Spot Scoring Method and Score-Based Fixing Guidance Generation
Yonghee PARK Junghoe CHOI Jisuk HONG Sanghoon LEE Moonhyun YOO Jundong CHO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3082-3085
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
physical designhot-spot detectioncalibrated scoring functionlayout fixing guidanceprocess window
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Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model
Yanming JIA Yici CAI Xianlong HONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3783-3792
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
VLSIbuffer insertionphysical designDFMdummy fill
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Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model
Hidenari NAKASHIMA Junpei INOUE Kenichi OKADA Kazuya MASU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3358-3366
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Prediction and Analysis
Keyword: 
interconnectlayout compactionphysical designplacementcore utilization
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Efficient Routing of Board-Level Optical Clocks for Ultra High-Speed Systems
Chung-Seok (Andy) SEO Abhijit CHATTERJEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/06/01
Vol. E87-A  No. 6 ; pp. 1310-1317
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003))
Category: 
Keyword: 
clockoptical waveguideinterconnectphysical designoptimization
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