Efficient Sequential Architecture of AES CCM for the IEEE 802.16e

Jae Deok JI  Seok Won JUNG  Jongin LIM  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E95-D   No.1   pp.185-187
Publication Date: 2012/01/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E95.D.185
Print ISSN: 0916-8532
Type of Manuscript: Special Section LETTER (Special Section on Trust, Security and Privacy in Computing and Communication Systems)
Category: Privacy
Keyword: 
cryptography,  communication system security,  integrated chip design,  FPGA,  

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Summary: 
In this paper, we propose efficient sequential AES CCM architecture for the IEEE 802.16e. In the proposed architecture, only one AES encryption core is used and the operation of the CTR and the CBC-MAC is processed concurrently within one round. With this design approach, we can design sequential AES CCM architecture having 570 Mbps@102.4 MHz throughput and 1,397 slices at a Spartan3 3s5000 device.