A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations

Kazuya KATSUKI  Manabu KOTANI  Kazutoshi KOBAYASHI  Hidetoshi ONODERA  

IEICE TRANSACTIONS on Electronics   Vol.E90-C    No.4    pp.699-707
Publication Date: 2007/04/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.4.699
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Digital
within-die variation,  reconfigurable device,  FPGA,  LUT (look-up table),  yield,  

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In this paper, we show that speed and yield of reconfigurable devices can be enhanced by utilizing within-die (WID) delay variations. An LUT Array LSI is fabricated to confirm whether FPGAs have clear WID variations to be utilized. We can measure delay variations by counting the number of LUTs a signal propagates within a certain time. Clear die-to-die (D2D) and WID variations are observed. We propose a variation model from the measurement results. Adequacy of the model is discussed from randomness of the random component. Effect of the speed and yield enhancement is confirmed using the proposed model. Yield increases from 80.0% to 100.0% by optimizing configurations.