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| Keyword : PLL
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Modulation Configurations of Phase Locked Loops for High-Speed and High-Precision Wired and Wireless Applications
Masaru KOKUBO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2023/05/01
Vol. E106-A
No. 5 ;
pp. 817-822
Type of Manuscript:
INVITED PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category:
Keyword:
PLL, modulation, communications, integrated circuits, | | | Summary | Full Text:PDF | |
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Injection Locked Charge-Pump PLL with a Replica of the Ring Oscillator
Jeonghoon HAN Masaya MIYAHARA Akira MATSUZAWA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C
No. 4 ;
pp. 316-324
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
Injection-lock, ring oscillator, lock range, PLL, | | | Summary | Full Text:PDF | |
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Digital-Centric RF CMOS Technologies
Akira MATSUZAWA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2008/11/01
Vol. E91-C
No. 11 ;
pp. 1720-1725
Type of Manuscript:
INVITED PAPER (Special Section on Microwave and Millimeter-wave Technologies)
Category:
Keyword:
CMOS, RF, analog, digital, tuner, PLL, sampling, mixer, wireless, | | | Summary | Full Text:PDF | |
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A Fast-Lock DLL with Power-On Reset Circuit
Kuo-Hsing CHENG Yu-Lung LO Shu-Yu JIANG | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/09/01
Vol. E87-A
No. 9 ;
pp. 2210-2220
Type of Manuscript:
Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category:
Keyword:
DLL, PLL, POR, fast lock, multiphase outputs, | | | Summary | Full Text:PDF | |
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A Clock and Data Recovery PLL for Variable Bit Rate NRZ Data Using Adaptive Phase Frequency Detector
Gijun IDEI Hiroaki KUNIEDA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C
No. 6 ;
pp. 956-963
Type of Manuscript:
Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category:
Keyword:
capture range, CCO, CDR, clock and data recovery, false lock, jitter, NRZ, PFD, PLL, VCO, z-domain analysis, | | | Summary | Full Text:PDF | |
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A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance
Takeo YASUDA Hiroaki FUJITA Hidetoshi ONODERA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A
No. 11 ;
pp. 2793-2801
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Analog Design
Keyword:
PLL, phase adjust, variable delay, lock-up, | | | Summary | Full Text:PDF | |
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A 3.3 V CMOS PLL with a Self-Feedback VCO
Yeon Kug MOON Kwang Sub YOON | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A
No. 12 ;
pp. 2623-2626
Type of Manuscript:
Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Analog Circuit Design
Keyword:
PLL, self-feedback VCO, CMOS, DC-DC voltage up/down converter, | | | Summary | Full Text:PDF | |
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High-Speed Wide-Locking Range VCO with Frequency Calibration
Takeo YASUDA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A
No. 12 ;
pp. 2616-2622
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Analog Circuit Design
Keyword:
VCO, PLL, high speed, wide locking range, calibration, | | | Summary | Full Text:PDF | |
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A 1.0 Gbps CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method
Jun-Young PARK Jin-Ku KANG | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A
No. 6 ;
pp. 1100-1105
Type of Manuscript:
Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category:
Keyword:
oversampling data recovery, PLL, DLL, jitter, | | | Summary | Full Text:PDF | |
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High-Speed, Low-Power Lightwave Communication ICs Using InP/InGaAs Double-Heterojunction Bipolar Transistors
Eiichi SANO Kenji KURISHIMA Hiroki NAKAJIMA Shoji YAMAHATA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1999/11/25
Vol. E82-C
No. 11 ;
pp. 2000-2006
Type of Manuscript:
Special Section PAPER (Special Issue on High-Frequency/High-Speed Devices for Information and Communication Systems in the 21st Century)
Category: Low Power-Consumption RF ICs
Keyword:
InP, HBT, amplifier, flip-flop, PLL, | | | Summary | Full Text:PDF | |
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A 0.25 µm CMOS/SIMOX PLL Clock Generator Embedded in a Gate Array LSI with a Locking Range of 5 to 500 MHz
Hiroki SUTOH Kimihiro YAMAKOSHI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1999/07/25
Vol. E82-C
No. 7 ;
pp. 1334-1340
Type of Manuscript:
PAPER
Category: Integrated Electronics
Keyword:
PLL, CMOS/SIMOX, VCO, clock, jitter, skew, lock range, | | | Summary | Full Text:PDF | |
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Dual-Loop Digital PLL Design for Adaptive Clock Recovery
Tae Hun KIM Beomsup KIM | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A
No. 12 ;
pp. 2509-2514
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Transistor-level Circuit Analysis, Design and Verification
Keyword:
digital PLL, DPLL, PLL, adaptive algorithm, clock recovery, | | | Summary | Full Text:PDF | |
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Optimal Loop Bandwidth Design for Low Noise PLL Applications
Kyoohyun LIM Seung Hee CHOI Beomsup KIM | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A
No. 10 ;
pp. 1979-1985
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
optimal bandwidth, PLL, jitter, low noise, | | | Summary | Full Text:PDF | |
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Calculation of Harmonic Distortion of PLL FM Demodulator with Time Delay
Yutaka TAKAHASHI Hitoshi SAKAGAMI | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 1995/09/25
Vol. E78-B
No. 9 ;
pp. 1336-1338
Type of Manuscript:
LETTER
Category: Communication Systems and Transmission Equipment
Keyword:
PLL, distortion, delay, demodulator, | | | Summary | Full Text:PDF | |
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A PLL-Based Programmable Clock Generator with 50-to 350-MHz Oscillating Range for Video Signal Processors
Junichi GOTO Masakazu YAMASHINA Toshiaki INOUE Benjamin S. SHIH Youichi KOSEKI Tadahiko HORIUCHI Nobuhisa HAMATAKE Kouichi KUMAGAI Tadayoshi ENOMOTO Hachiro YAMADA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C
No. 12 ;
pp. 1951-1956
Type of Manuscript:
Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Processor Interfaces
Keyword:
electronic circuits, clock generator, PLL, frequency multiplication, VCO, VCO gain, jitter, pull-in range, CMOS, VSP, | | | Summary | Full Text:PDF | |
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The Homoclinic Points and Chaos from Phase–Locked Loops with Large Damping
Tetsuro ENDO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A
No. 11 ;
pp. 1764-1770
Type of Manuscript:
Special Section PAPER (Special Section on Nonlinear Theory and Its Applications)
Category: Analysis of Phase Locked Loops
Keyword:
PLL, chaos homoclinic points, Melnikov method, large damping, | | | Summary | Full Text:PDF | |
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A Study of a MOS VCO Circuit by Using a Current–Controlled Differential Delay Cell
Yasuhiro SUGIMOTO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A
No. 11 ;
pp. 1929-1931
Type of Manuscript:
Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Spring Conference)
Category:
Keyword:
MOS analog circuit, PLL, VCO, current control, differential delay cell, | | | Summary | Full Text:PDF | |
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High Speed DRAMs with Innovative Architectures
Shigeo OHSHIMA Tohru FURUYAMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C
No. 8 ;
pp. 1303-1315
Type of Manuscript:
INVITED PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword:
DRAM, memory bottleneck, data bandwidth, latency, synchronous DRAM, pipeline architecture, data prefetching, cache DRAM, fast copyback, Rambus interface, Rambus DRAM, protocol packet, PLL, | | | Summary | Full Text:PDF | |
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A Self Frequency Preset PLL Synthesizer
Kazuhiko SEKI Shuzo KATO | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 1993/05/25
Vol. E76-B
No. 5 ;
pp. 473-479
Type of Manuscript:
Special Section PAPER (Special Issue on Satellite Communications Networking and Applications)
Category:
Keyword:
PLL, synthesizer, preset, TDMA, frequency hopping, | | | Summary | Full Text:PDF | |
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High Resolution and Fast Frequency Settling PLL Synthesizer
Kazuhiko SEKI Masahiro MORIKURA Shuzo KATO | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 1992/08/25
Vol. E75-B
No. 8 ;
pp. 739-746
Type of Manuscript:
Special Section PAPER (Special Issue on the 4th Japan-Korea Joint Conference on Communications, Networks, Switching Systems and Satellite Communications (4th JC-CNSS))
Category:
Keyword:
PLL, synthesizer, DDS, TDMA, frequency hopping, | | | Summary | Full Text:PDF | |
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