Optimized Charge Pump and Nonlinear Phase Frequency Detector for a Ka-Band Phase-Locked Loop in 90-nm CMOS Process

Lu TANG  Zhigong WANG  Tiantian FAN  Faen LIU  Changchun ZHANG  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E102-C   No.11   pp.825-832
Publication Date: 2019/11/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.2019ECP5007
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword: 
PLL,  charge pump,  phase frequency detector,  CMOS process,  

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Summary: 
In this paper, an improved charge pump (CP) and a modified nonlinear phase frequency detector (PFD) are designed and fabricated in a 90-nm CMOS process. The CP is optimized with a combination of circuit techniques such as pedestal error cancel scheme to eliminate the charge injection and the other non-ideal characteristics. The nonlinear PFD is based on a modified circuit topology to enhance the acquisition capability of the PLL. The optimized CP and nonlinear PFD are integrated into a Ka-band PLL. The measured output current mismatch ratio of the improved CP is less than 1% when the output voltage Vout fluctuates between 0.2 to 1.1V from a 1.2V power supply. The measured phase error detection range of the modified nonlinear PFD is between -2π and 2π. Owing to the modified CP and PFD, the measured reference spur of the Ka-band PLL frequency synthesizer containing the optimized CP and PFD is only -56.409dBc at 30-GHz at the locked state.