Chin-Cheng KUO

A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application
Kuo-Hsing CHENG Yu-Chang TSAI Chien-Nan Jimmy LIU Kai-Wei HONG Chin-Cheng KUO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/07/01
Vol. E92-C  No. 7  pp. 964-972
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
phase-locked loop (PLL), self-calibration, low jitter, multi-phase VCO, 
 Summary | Full Text:PDF
An Efficient Approach to Build Accurate Behavioral Models of PLL Designs
Chin-Cheng KUO Yu-Chien WANG Chien-Nan Jimmy LIU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/02/01
Vol. E89-A  No. 2  pp. 391-398
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
analog behavioral model, PLL, IP, bottom-up extraction, 
 Summary | Full Text:PDF