A 3.3 V CMOS PLL with a Self-Feedback VCO

Yeon Kug MOON  Kwang Sub YOON  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E83-A   No.12   pp.2623-2626
Publication Date: 2000/12/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Analog Circuit Design
PLL,  self-feedback VCO,  CMOS,  DC-DC voltage up/down converter,  

Full Text: PDF>>
Buy this Article

A 3.3 V CMOS PLL (Phase Locked loop) with a self-feedback VCO (Voltage Controlled Oscillator) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage-to-frequency linearity of VCO with a new delay cell. The proposed VCO with a self-feedback path operates at a wide frequency range of 30 MHz-1 GHz with a good linearity. The DC-DC Voltage Up/Down Converter is newly designed to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6 µm n-well CMOS process. The simulation results illustrate a locking time of 2.6 µsec at 1 GHz, lock in range of 100 MHz-1 GHz, and a power dissipation of 112 mW.