For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Low Supply Voltage and Low-Power 1-GHz PLL Frequency Synthesizer for Mobile Terminals
Masaru KOKUBO Yoshiyuki SHIBAHARA Hirokazu AOKI Changku HWANG
IEICE TRANSACTIONS on Electronics
Publication Date: 2003/01/01
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
PLL, VCO, charge-pump, dynamic output stage, stability,
Full Text: PDF>>
We introduce a PLL (Phase Locked Loop) for low-power and a low supply voltage applications. Because the PLL is a key device of the system LSIs used in mobile terminals, it is very important that PLLs operate under a low supply voltage to reduce power consumption. We investigate the limitations of the conventional VCO that we proposed in Ref. and propose a modified VCO that uses common load transistors. Furthermore, we propose a charge pump that uses a dynamic output stage op-amp and a stability technique for the CMOS process, and it does not contain any special resistors. The results of an evaluation of a device fabricated using a standard logic 0.18-µm CMOS process demonstrated that the proposed PLL operated above 1.0 GHz with a 1.2-V supply voltage and it produced only a small amount of jitter that was lower than 78 psp-p.