IEICE Trans - A 0.25 µm CMOS/SIMOX PLL Clock Generator Embedded in a Gate Array LSI with a Locking Range of 5 to 500 MHz

A 0.25 µm CMOS/SIMOX PLL Clock Generator Embedded in a Gate Array LSI with a Locking Range of 5 to 500 MHz

Hiroki SUTOH  Kimihiro YAMAKOSHI

Publication
IEICE TRANSACTIONS on Electronics   Vol.E82-C    No.7    pp.1334-1340
Publication Date: 1999/07/25
Online ISSN:
DOI:
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword:
PLL,  CMOS/SIMOX,  VCO,  clock,  jitter,  skew,  lock range,

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Summary:
This paper describes a wide-frequency-range phase-locked-loop (PLL) clock generator embedded in a gate array LSI using 0.25 µm CMOS/SIMOX technology. The four ratios of internal clock frequency to external clock frequency this generator supports are 2, 4, 8, and 16. The PLL has two kinds of voltage-controlled oscillators that are selected automatically according to the frequency so as to widen the operating frequency range while keeping jitter low. Measured results show that the PLL operates with a lock range from 5 to 500 MHz. At 500 MHz, the peak-to-peak jitter is 50 ps. The supply voltage is 2 V and power dissipation is less than 14 mW. At a supply voltage of 2 V, the maximum operating frequency of 0.25 µm CMOS/SIMOX PLL is 30% higher than that of 0.25 µm bulk CMOS PLL.