A Near-Threshold Cell-Based All-Digital PLL with Hierarchical Band-Selection G-DCO for Fast Lock-In and Low-Power Applications Chia-Wen CHANGYuan-Hua CHUShyh-Jye JOU
Techniques for Widening Lock and Pull-in Ranges and Suppressing Jitter in Clock and Data Recovery ICs--Duplicated Loop Control CDR-- Keiji KISHINENoboru ISHIHARAHaruhiko ICHINO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/04/01 Vol. E84-CNo. 4 ;
pp. 460-469 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: clock and data recovery, PLL, duplicated loop, low jitter, 2.5-Gb/s,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/12/25 Vol. E80-CNo. 12 ;
pp. 1560-1571 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies) Category: Keyword: phase-locked loop, low voltage, low jitter, fast-lock time,
