A Clock and Data Recovery PLL for Variable Bit Rate NRZ Data Using Adaptive Phase Frequency Detector

Gijun IDEI  Hiroaki KUNIEDA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E87-C   No.6   pp.956-963
Publication Date: 2004/06/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
capture range,  CCO,  CDR,  clock and data recovery,  false lock,  jitter,  NRZ,  PFD,  PLL,  VCO,  z-domain analysis,  

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Summary: 
An adaptive 4-state phase-frequency detector (PFD) for clock and data recovery (CDR) PLL of non return to zero (NRZ) data is presented. The PLL achieves false-lock free operation with rapid frequency-capture and wide bit-rate-capture range. The variable bit rate operation is achieved by adaptive delay control of data delay. Circuitry and overall architecture are described in detail. A z-Domain analysis is also presented.