An Efficient Approach to Build Accurate Behavioral Models of PLL Designs

Chin-Cheng KUO  Yu-Chien WANG  Chien-Nan Jimmy LIU  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E89-A   No.2   pp.391-398
Publication Date: 2006/02/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e89-a.2.391
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
analog behavioral model,  PLL,  IP,  bottom-up extraction,  

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In this paper, an efficient bottom-up extraction approach is presented to generate accurate behavioral models of PLL designs more quickly by using Verilog-AMS language. The main idea is to use a special "characterization mode" such that we can use only one input pattern to get all required circuit parameters with parasitic effects. After carefully adjustment, all parameters in our behavioral models can be measured at the outputs of the PLL system without simulating each block separately. Therefore, this approach is more suitable to accurately model protected IPs or flattened post-layout netlists. In the experimental results, we will build an accurate PLL behavioral model for demonstration and compare the results with HSPICE simulation and traditional behavioral models.