High Resolution and Fast Frequency Settling PLL Synthesizer

Kazuhiko SEKI
Shuzo KATO

IEICE TRANSACTIONS on Communications   Vol.E75-B    No.8    pp.739-746
Publication Date: 1992/08/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the 4th Japan-Korea Joint Conference on Communications, Networks, Switching Systems and Satellite Communications (4th JC-CNSS))
PLL,  synthesizer,  DDS,  TDMA,  frequency hopping,  

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This paper proposes a high resolution and fast frequency settling PLL synthesizer for frequency hopping radio communication equipment. The proposed synthesizer enables the carrier frequency to be changed within the duration of a burst signal and yields higher frequency resolution than the reference signal frequency. To reduce frequency settling time without degradation of frequency resolution and phase noise, this paper proposes a new phase and frequency preset (PEP) PLL synthesizer which employs a digital phase accumulator to generate high resolution reference signal. Experimental results show that the settling time of a prototype synthesizer is less than 300µs while spurious signals are suppressed by more than 55 dB. In comparison with conventional PLL synthesizers, the frequency settling time is reduced by 80%. Furthermore, the higher frequency resolution than the reference signal is successfully demonstrated. Therefore, the proposed PFP PLL synthesizer with the digital reference signal can achieve the output signal with high frequency resolution less than 1Hz.