Woo-Young CHOI


Demonstration of 60-GHz Link Using a 1.6-Gb/s Mixed-Mode BPSK Demodulator
Kwang-Chun CHOI Minsu KO Duho KIM Woo-Young CHOI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/12/01
Vol. E93-C  No. 12  pp. 1704-1707
Type of Manuscript:  BRIEF PAPER
Category: Electronic Circuits
Keyword: 
binary phase shift keyingBPSKmodemdemodulatorIEEE802.15.3cwireless PAN
 Summary | Full Text:PDF

Linear Analysis of Feedforward Ring Oscillators
Young-Seok PARK Pyung-Su HAN Woo-Young CHOI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/09/01
Vol. E93-C  No. 9  pp. 1467-1470
Type of Manuscript:  BRIEF PAPER
Category: Electronic Circuits
Keyword: 
feedforward ring oscillatorring oscillatoroscillator analysis
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A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator
Chang-Kyung SEONG Seung-Woo LEE Woo-Young CHOI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2008/05/01
Vol. E91-B  No. 5  pp. 1397-1402
Type of Manuscript:  PAPER
Category: Devices/Circuits for Communications
Keyword: 
burst-modeclock and data recovery circuitdigital phase alignerphase interpolator
 Summary | Full Text:PDF

A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution
Chang-Kyung SEONG Seung-Woo LEE Woo-Young CHOI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/01/01
Vol. E90-C  No. 1  pp. 165-170
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
dual-loop clock and data recovery (CDR)phase interpolatorphase resolution
 Summary | Full Text:PDF

A 0.18 µm CMOS 3.125-Gb/s Digitally Controlled Adaptive Line Equalizer with Feed-Forward Swing Control for Backplane Serial Link
Ki-Hyuk LEE Jae-Wook LEE Woo-Young CHOI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/10/01
Vol. E89-C  No. 10  pp. 1454-1459
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
adaptive equalizerbackplane transceiver
 Summary | Full Text:PDF

Novel 622 Mb/s Burst-Mode Clock and Data Recovery Circuits with Muxed Oscillators
Yu-Gun KIM Chun-Oh LEE Seung-Woo LEE Hyun-Su CHAI Hyun-Suk RYU Woo-Young CHOI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2003/11/01
Vol. E86-B  No. 11  pp. 3288-3292
Type of Manuscript:  LETTER
Category: Communication Devices/Circuits
Keyword: 
burst-modePLLCDRPON
 Summary | Full Text:PDF

A Giga-b/s CMOS Clock and Data Recovery Circuit with a Novel Adaptive Phase Detector
Jae-Wook LEE Cheon-O LEE Woo-Young CHOI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2003/07/01
Vol. E86-B  No. 7  pp. 2186-2189
Type of Manuscript:  LETTER
Category: Communication Devices/Circuits
Keyword: 
clock and data recoveryphase detectorphase locked loop
 Summary | Full Text:PDF

A New Charge Pump PLL with Reduced Jitter
Yu-Gun KIM Myoung-Su LEE Woo-Young CHOI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2001/06/01
Vol. E84-B  No. 6  pp. 1680-1682
Type of Manuscript:  LETTER
Category: Communication Devices/Circuits
Keyword: 
charge pumpphase-locked loop (PLL)jitter characteristics
 Summary | Full Text:PDF