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| Keyword : SRAM
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A SOI Cache-Tag Memory with Dual-Rail Wordline Scheme
Nobutaro SHIBATA Takako ISHIHARA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2016/02/01
Vol. E99-C
No. 2 ;
pp. 316-330
Type of Manuscript:
PAPER
Category: Integrated Electronics
Keyword:
4-way set-associative, cache-tag, CMOS, directed graph, dual-rail wordline, FD-SOI, I/O-separated memory cell, LRU, NRZ-type write-enable signal, SIMOX, SRAM, | | | Summary | Full Text:PDF | |
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A Low-Cost VLSI Architecture of Multiple-Size IDCT for H.265/HEVC
Heming SUN Dajiang ZHOU Peilin LIU Satoshi GOTO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A
No. 12 ;
pp. 2467-2476
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword:
HEVC, IDCT, SRAM, area-efficient, video coding, | | | Summary | Full Text:PDF | |
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Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis
Shiho HAGIWARA Takanori DATE Kazuya MASU Takashi SATO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C
No. 4 ;
pp. 280-288
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
design for manufacturing, Monte Carlo method, importance sampling, SRAM, process variation, yield, norm minimization, Gaussian mixture models, clustering, hypersphere sampling, | | | Summary | Full Text:PDF | |
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Single-Grain Si Thin-Film Transistors for Monolithic 3D-ICs and Flexible Electronics
Ryoichi ISHIHARA Jin ZHANG Miki TRIFUNOVIC Jaber DERAKHSHANDEH Negin GOLSHANI Daniel M. R. TAJARI MOFRAD Tao CHEN Kees BEENAKKER Tatsuya SHIMODA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C
No. 4 ;
pp. 227-237
Type of Manuscript:
INVITED PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
silicon, thin-film transistor, 3D-ICs, excimer-laser, crystallization, SRAM, image sensor, flexible electronics, | | | Summary | Full Text:PDF | |
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A High Performance Current Latch Sense Amplifier with Vertical MOSFET
Hyoungjun NA Tetsuo ENDOH | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2013/05/01
Vol. E96-C
No. 5 ;
pp. 655-662
Type of Manuscript:
Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category:
Keyword:
current latch sense amplifier, vertical MOSFET, SRAM, sensing time, speed, current, voltage gain, stability, yield, circuit area, | | | Summary | Full Text:PDF | |
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Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier
Jinn-Shyan WANG Pei-Yao CHANG Chi-Chang LIN | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2012/01/01
Vol. E95-C
No. 1 ;
pp. 172-175
Type of Manuscript:
BRIEF PAPER
Category: Integrated Electronics
Keyword:
SRAM, subthreshold, variations, | | | Summary | Full Text:PDF | |
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A Large “Read” and “Write” Margins, Low Leakage Power, Six-Transistor 90-nm CMOS SRAM
Tadayoshi ENOMOTO Nobuaki KOBAYASHI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C
No. 4 ;
pp. 530-538
Type of Manuscript:
Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category:
Keyword:
SRAM, leakage power, “write” margin, “read” margin, | | | Summary | Full Text:PDF | |
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Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM
Masaaki IIJIMA Kayoko SETO Masahiro NUMA Akira TADA Takashi IPPOSHI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A
No. 12 ;
pp. 2691-2694
Type of Manuscript:
Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Memory Design and Test
Keyword:
PD-SOI, body-bias, SRAM, low power design, | | | Summary | Full Text:PDF | |
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Low-Voltage Embedded RAMs in Nanometer Era
Takayuki KAWAHARA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C
No. 4 ;
pp. 735-742
Type of Manuscript:
INVITED PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category:
Keyword:
low-voltage, SRAM, DRAM, FD-SOI, twin-cell, embedded RAM, | | | Summary | Full Text:PDF | |
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A Self-Alignment Row-by-Row Variable-VDD Scheme Reducing 90% of Active-Leakage Power in SRAM's
Fayez Robert SALIBA Hiroshi KAWAGUCHI Takayasu SAKURAI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C
No. 4 ;
pp. 743-748
Type of Manuscript:
Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Memory
Keyword:
active leakage, low power, SRAM, | | | Summary | Full Text:PDF | |
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