IEICE Trans

Nobutaro SHIBATA

An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines Nobutaro SHIBATA Mitsuo NAKAMURA
Publication: Publication Date: 2018/08/01 Vol. E101-A No. 8 pp. 1185-1196 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: ATE, delay-locked loop, digital-to-time converter, linearity error, on the fly, plain CMOS logic, timing jitter, timing vernier,
	Summary \| Full Text:PDF

A SOI Multi-V_DD Dual-Port SRAM Macro for Serial Access Applications Nobutaro SHIBATA Mayumi WATANABE Takako ISHIHARA
Publication: Publication Date: 2017/11/01 Vol. E100-C No. 11 pp. 1061-1068 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: 10T memory cell, CMOS, dual-port SRAM, FIFO memory, fully depleted SOI, look-ahead operation, multi-V_DD, serial access,
	Summary \| Full Text:PDF

A New High-Density 10T CMOS Gate-Array Base Cell for Two-Port SRAM Applications Nobutaro SHIBATA Yoshinori GOTOH Takako ISHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/06/01 Vol. E99-C No. 6 pp. 717-726 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: 10T type, bitline capacitance, CMOS, gate array, high speed, low power, memory-oriented base cell, shared contact, two-port SRAM,
	Summary \| Full Text:PDF

A SOI Cache-Tag Memory with Dual-Rail Wordline Scheme Nobutaro SHIBATA Takako ISHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/02/01 Vol. E99-C No. 2 pp. 316-330 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: 4-way set-associative, cache-tag, CMOS, directed graph, dual-rail wordline, FD-SOI, I/O-separated memory cell, LRU, NRZ-type write-enable signal, SIMOX, SRAM,
	Summary \| Full Text:PDF

A Sub-0.5 V Differential ED-CMOS/SOI Circuit with Over-1-GHz Operation Takakuni DOUSEKI Toshishige SHIMAMURA Nobutaro SHIBATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/04/01 Vol. E88-C No. 4 pp. 582-588 Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP) Category: Digital Keyword: ultralow voltage, high-speed, ED-MOS, multi-V_th CMOS, fully-depleted SOI,
	Summary \| Full Text:PDF

Current-Sensed SRAM Techniques for Megabit-Class Integration--Progress in Operating Frequency by Using Hidden Writing-Recovery Architecture-- Nobutaro SHIBATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/11/25 Vol. E82-C No. 11 pp. 2056-2064 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SRAM, high speed, writing-recovery, current sense, virtual-GND line, squashed memory cell,
	Summary \| Full Text:PDF

Megabit-Class Size-Configurable 250-MHz SRAM Macrocells with a Squashed-Memory-Cell Architecture Nobutaro SHIBATA Hiroshi INOKAWA Keiichiro TOKUNAGA Soichi OHTA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/01/25 Vol. E82-C No. 1 pp. 94-104 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SRAM, macrocell, size-configurable, high speed, low power, per-bitline architecture, current-sense amplifier, squashed memory cell, trench isolation,
	Summary \| Full Text:PDF

A Switched Virtual-GND Level Technique for Fast and Low Power SRAM's Nobutaro SHIBATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/12/25 Vol. E80-C No. 12 pp. 1598-1607 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SRAM, low power, virtual GND, column address, synchronous, macrocell,
	Summary \| Full Text:PDF

Current Sense Amplifiers for Low-Voltage Memories Nobutaro SHIBATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/08/25 Vol. E79-C No. 8 pp. 1120-1130 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SRAM, ROM, current sensing, amplifier, low voltage,
	Summary \| Full Text:PDF

A Low-Power Synchronous SRAM Macrocell with Latch-Type Fast Sense Circuits Nobutaro SHIBATA Mayumi WATANABE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/07/25 Vol. E78-C No. 7 pp. 797-804 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age) Category: Keyword: marcocell, memory, synchronous, low power, latch type,
	Summary \| Full Text:PDF

High-Performance Memory Macrocells with Row and Column Sliceable Architecture Nobutaro SHIBATA Yoshinori GOTOH Shigeru DATE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/11/25 Vol. E76-C No. 11 pp. 1641-1648 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Application Specific Memory Keyword: ASIC, CMOS, macrocell, memory, configurable, row sliceable, decoder, short design Turn-Around-Time (TAT),
	Summary \| Full Text:PDF