Fengfeng WU


Improved CRC Calculation Strategies for 64-bit Serial RapidIO
Fengfeng WU Song JIA Qinglong MENG Shigong LV Yuan WANG Dacheng ZHANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/10/01
Vol. E96-C  No. 10  pp. 1330-1338
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
RapidIOCyclic Redundancy Checkembedded interconnectionparallel CRCCRC slicing
 Summary | Full Text:PDF

Data Convertors Design for Optimization of the DDPL Family
Song JIA Li LIU Xiayu LI Fengfeng WU Yuan WANG Ganggang ZHANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/09/01
Vol. E96-C  No. 9  pp. 1195-1200
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
convertordifferential power analysis (DPA)information securitydelay-based dual-rail precharge logic (DDPL)low power
 Summary | Full Text:PDF

A Current-Mirror Winner-Take-All Sense Amplifier for Low Voltage SRAMs
Song JIA Heqing XU Fengfeng WU Yuan WANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/09/01
Vol. E96-C  No. 9  pp. 1205-1207
Type of Manuscript:  BRIEF PAPER
Category: Integrated Electronics
Keyword: 
SRAMsense amplifierwinner-take-allhigh speed
 Summary | Full Text:PDF